公开(公告)号：US07444632B2

公开(公告)日：2008-10-28

申请号：US10670826

申请日：2003-09-25

Applicant: Barry L Minor ,  Mark Richard Nutter ,  VanDung Dang To

Inventor： Barry L Minor ,  Mark Richard Nutter ,  VanDung Dang To

IPC: G06F9/46 ,  G06F9/44

CPC classification number: G06F9/5044

Abstract: Source code subtasks are compiled into byte code subtasks whereby the byte code subtasks are translated into processor-specific object code subtasks at runtime. The processor-type selection is based upon one of three approaches which are 1) a brute force approach, 2) higher-level approach, or 3) processor availability approach. Each object code subtask is loaded in a corresponding processor type for execution. In one embodiment, a compiler stores a pointer in a byte code file that references the location of a byte code subtask. In this embodiment, the byte code subtask is stored in a shared library and, at runtime, a runtime loader uses the pointer to identify the location of the byte code subtask in order to translate the byte code subtask.

Abstract translation: 源代码子任务被编译成字节代码子任务，从而在运行时将字节代码子任务转换为处理器特定目标代码子任务。 处理器类型选择基于以下三种方法之一：1）强力方法，2）较高级别的方法，或3）处理器可用性方法。 每个对象代码子任务都以相应的处理器类型加载以执行。 在一个实施例中，编译器将指针存储在引用字节代码子任务的位置的字节代码文件中。 在本实施例中，字节代码子任务存储在共享库中，并且在运行时，运行时加载器使用指针来标识字节代码子任务的位置，以便翻译字节代码子任务。

公开(公告)号：US07389508B2

公开(公告)日：2008-06-17

申请号：US10670833

申请日：2003-09-25

Applicant: Maximino Aguilar, Jr. ,  Michael Norman Day ,  Mark Richard Nutter ,  James Xenidis

Inventor： Maximino Aguilar, Jr. ,  Michael Norman Day ,  Mark Richard Nutter ,  James Xenidis

IPC: G06F9/46 ,  G06F12/00 ,  G06F13/00

CPC classification number: G06F9/5061 ,  G06F2209/5012

Abstract: A system and method for grouping processors is presented. A processing unit (PU) initiates an application and identifies the application's requirements. The PU assigns one or more synergistic processing units (SPUs) and a memory space to the application in the form of a group. The application specifies whether the task requires shared memory or private memory. Shared memory is a memory space that is accessible by the SPUs and the PU. Private memory, however, is a memory space that is only accessible by the SPUs that are included in the group. When the application executes, the resources within the group are allocated to the application's execution thread. Each group has its own group properties, such as address space, policies (i.e. real-time, FIFO, run-to-completion, etc.) and priority (i.e. low or high). These group properties are used during thread execution to determine which groups take precedence over other tasks.

Abstract translation: 提出了一种用于分组处理器的系统和方法。 处理单元（PU）启动应用程序并识别应用程序的要求。 PU以组的形式向应用分配一个或多个协同处理单元（SPU）和存储器空间。 应用程序指定任务是否需要共享内存或专用内存。 共享内存是可由SPU和PU访问的内存空间。 然而，专用内存是只能由组中包含的SPU访问的内存空间。 当应用程序执行时，组内的资源被分配给应用程序的执行线程。 每个组都有自己的组属性，如地址空间，策略（即实时，FIFO，运行完成等）和优先级（即低或高）。 在线程执行期间使用这些组属性来确定哪些组优先于其他任务。

公开(公告)号：US07389352B2

公开(公告)日：2008-06-17

申请号：US10747704

申请日：2003-12-24

Applicant: Daryl Carvis Cromer ,  Philip John Jakes ,  Howard Jeffrey Locker ,  Michael T. Vanover

Inventor： Daryl Carvis Cromer ,  Philip John Jakes ,  Howard Jeffrey Locker ,  Michael T. Vanover

IPC: G06F13/00

CPC classification number: H04W76/15 ,  H04W52/0219 ,  H04W84/12 ,  H04W84/18 ,  H04W88/06 ,  Y02D70/142 ,  Y02D70/144 ,  Y02D70/22

Abstract: A system and method for concurrent WLAN and WPAN wireless modes from a single device is presented. A client uses a Wi-Fi device's infrastructure mode to communicate in a WLAN environment and, during idle WLAN times, uses the Wi-Fi device's adhoc mode to communicate in a WPAN environment. The Wi-Fi device uses a watchdog timer to switch between infrastructure mode and adhoc mode. When the client's Wi-Fi device switches to infrastructure mode, the client's Wi-Fi device uses an infrastructure register and an infrastructure device driver to transfer data over the WLAN environment. Likewise, when the client's Wi-Fi device switches to adhoc mode, the client's Wi-Fi device uses an adhoc register and an adhoc device driver to transfer data over the WLAN environment. The client uses a code shim to act as a virtual device driver at times when either the infrastructure device driver or the adhoc device driver is inactive.

Abstract translation: 提出了一种用于从单个设备并发WLAN和WPAN无线模式的系统和方法。 客户端使用Wi-Fi设备的基础设施模式在WLAN环境中进行通信，并且在空闲WLAN时间期间，使用Wi-Fi设备的自组织模式在WPAN环境中进行通信。 Wi-Fi设备使用看门狗定时器在基础设施模式和自适应模式之间切换。 当客户端的Wi-Fi设备切换到基础架构模式时，客户端的Wi-Fi设备使用基础结构寄存器和基础架构设备驱动程序通过WLAN环境传输数据。 同样，当客户端的Wi-Fi设备切换到自适应模式时，客户端的Wi-Fi设备会使用adhoc寄存器和adhoc设备驱动程序通过WLAN环境传输数据。 在基础设施设备驱动程序或自组织设备驱动程序处于非活动状态时，客户端会使用代码填充作为虚拟设备驱动程序。

公开(公告)号：US07376795B2

公开(公告)日：2008-05-20

申请号：US11260833

申请日：2005-10-27

Applicant: Vaijayanthiamala K. Anand ,  Sandra K. Johnson ,  Kimberly DaShawn Simon

Inventor： Vaijayanthiamala K. Anand ,  Sandra K. Johnson ,  Kimberly DaShawn Simon

IPC: G06F13/00

CPC classification number: G06F12/0831

Abstract: A memory coherence protocol is provided for using cache line access frequencies to dynamically switch from an invalidation protocol to an update protocol. A frequency access count (FAC) is associated with each line of data in a memory area, such as each cache line in a private cache corresponding to a CPU in a multiprocessor system. Each time the line is accessed, the FAC associated with the line is incremented. When the CPU, or process, receives an invalidate signal for a particular line, the CPU checks the FAC for the line. If the CPU, or process, determines that it is a frequent accessor of a particular line that has been modified by another CPU, or process, the CPU sends an update request in order to obtain the modified data. If the CPU is not a frequent accessor of a line that has been modified, the line is simply invalidated in the CPU's memory area. By dynamically switching from an invalidate protocol to an update protocol, based on cache line access frequencies, efficiency is maintained while cache misses are minimized. Preferably, all FACs are periodically reset in order to ensure that the most recent cache line access data in considered.

Abstract translation: 提供了存储器一致性协议，用于使用高速缓存线路接入频率从无效协议动态地切换到更新协议。 频率访问计数（FAC）与存储器区域中的每一行数据相关联，诸如与多处理器系统中的CPU对应的专用高速缓存行中的每个高速缓存线。 每次访问线路时，与线路相关联的FAC将增加。 当CPU或进程接收到特定行的无效信号时，CPU会检查FAC是否为该行。 如果CPU或进程确定它是由另一个CPU或进程修改的特定行的频繁访问器，则CPU发送更新请求以获得修改的数据。 如果CPU不是经过修改的行的频繁访问器，则该行在CPU的内存区域中简单无效。 通过从无效协议动态切换到更新协议，基于高速缓存行接入频率，保持高速缓存未命中最小化的效率。 优选地，所有FAC都被周期性地复位，以便确保最新的高速缓存行访问所考虑的数据。

公开(公告)号：US07360218B2

公开(公告)日：2008-04-15

申请号：US10671132

申请日：2003-09-25

Applicant: Jos Manuel Accapadi ,  Andrew Dunshea ,  Dirk Michel ,  Mysore Sathyanarayana Srinivas

Inventor： Jos Manuel Accapadi ,  Andrew Dunshea ,  Dirk Michel ,  Mysore Sathyanarayana Srinivas

IPC: G06F9/455 ,  G06F9/46 ,  G06F9/00 ,  G06F9/30

CPC classification number: G06F9/4881 ,  G06F2209/483

Abstract: A system and method for identifying compatible threads in a Simultaneous Multithreading (SMT) processor environment is provided by calculating a performance metric, such as cycles per instruction (CPI), that occurs when two threads are running on the SMT processor. The CPI that is achieved when both threads were executing on the SMT processor is determined. If the CPI that was achieved is better than the compatibility threshold, then information indicating the compatibility is recorded. When a thread is about to complete, the scheduler looks at the run queue from which the completing thread belongs to dispatch another thread. The scheduler identifies a thread that is (1) compatible with the thread that is still running on the SMT processor (i.e., the thread that is not about to complete), and (2) ready to execute. The CPI data is continually updated so that threads that are compatible with one another are continually identified.

Abstract translation: 通过计算在SMT处理器上运行两个线程时发生的性能指标（例如每个指令周期（CPI）），可以提供用于在同时多线程（SMT）处理器环境中识别兼容线程的系统和方法。 确定在两个线程在SMT处理器上执行时实现的CPI。 如果实现的CPI优于兼容性阈值，则记录指示兼容性的信息。 当线程即将完成时，调度程序将查看完成线程所属的运行队列，以调度另一个线程。 调度程序标识（1）与SMT处理器上仍然运行的线程（即，即将完成的线程）兼容的线程，以及（2）准备执行。 持续更新CPI数据，以便不断地识别彼此兼容的线程。

公开(公告)号：US07321950B2

公开(公告)日：2008-01-22

申请号：US11050021

申请日：2005-02-03

Applicant: Mark David Bellows ,  Paul Allen Ganfield ,  Kent Harold Haselhorst ,  Ryan Abel Heckendorf ,  Tolga Ozguner

Inventor： Mark David Bellows ,  Paul Allen Ganfield ,  Kent Harold Haselhorst ,  Ryan Abel Heckendorf ,  Tolga Ozguner

IPC: G06F12/00

CPC classification number: G06F13/161 ,  G06F13/1647

Abstract: A method and apparatus for managing write-to-read turnarounds in an early read after write memory system are presented. Memory controller logic identifies a write operation's bank set, allows a different bank set read operation to issue prior to the write operation's completion, and allows a same bank set read operation to issue once the write operation completes. The memory controller includes operation counter logic, operation selection logic, operation acceptance logic, command formatting logic, and memory interface logic. The operation counter logic receives new-operation-related signals from the operation acceptance logic and, in turn, provides signals to the operation selection logic and the operation acceptance logic as to when to issue a read operation that corresponds to either an even DRAM bank or an odd DRAM bank.

Abstract translation: 提出了一种用于在写入存储器系统之后的早期读取中管理写入到读取周转的方法和装置。 存储器控制器逻辑识别写入操作的存储体组，允许在写入操作完成之前发出不同的存储体读取操作，并且一旦写入操作完成，就允许执行相同的存储体读取操作。 存储器控制器包括操作计数器逻辑，操作选择逻辑，操作接受逻辑，命令格式化逻辑和存储器接口逻辑。 操作计数器逻辑接收来自操作接受逻辑的新操作相关信号，并且继而向操作选择逻辑和操作接受逻辑提供关于什么时候发出对应于偶数DRAM组的读操作的信​​号 一个奇怪的DRAM银行。

公开(公告)号：US07290112B2

公开(公告)日：2007-10-30

申请号：US10955093

申请日：2004-09-30

Applicant: Maximino Aguilar, Jr. ,  Michael Norman Day ,  Mark Richard Nutter ,  James Xenidis

Inventor： Maximino Aguilar, Jr. ,  Michael Norman Day ,  Mark Richard Nutter ,  James Xenidis

IPC: G06F12/00

CPC classification number: G06F12/109 ,  G06F12/0284 ,  G06F12/1045

Abstract: A system and method for virtualization of processor resources is presented. A thread is created on a processor and the processor's local memory is mapped into an effective address space. In doing so, the processor's local memory is accessible by other processors, regardless of whether the processor is running. Additional threads create additional local memory mappings into the effective address space. The effective address space corresponds to either a physical local memory or a “soft” copy area. When the processor is running, a different processor may access data that is located in the first processor's local memory from the processor's local storage area. When the processor is not running, a softcopy of the processor's local memory is stored in a memory location (i.e. locked cache memory, pinned system memory, virtual memory, etc.) for other processors to continue accessing.

Abstract translation: 提出了一种用于处理器资源虚拟化的系统和方法。 在处理器上创建线程，并将处理器的本地内存映射到有效的地址空间。 这样做，处理器的本地内存可以由其他处理器访问，无论处理器是否正在运行。 附加线程会在有效地址空间中创建额外的本地内存映射。 有效地址空间对应于物理本地存储器或“软”复制区域。 当处理器运行时，不同的处理器可以从处理器的本地存储区域访问位于第一处理器的本地存储器中的数据。 当处理器未运行时，处理器的本地存储器的软拷贝存储在其他处理器的存储器位置（即锁定的高速缓冲存储器，固定的系统存储器，虚拟存储器等）中以继续访问。

公开(公告)号：US07187389B2

公开(公告)日：2007-03-06

申请号：US09833418

申请日：2001-04-12

Applicant: Sarah D. Redpath ,  Randy A. Rendahl ,  Robert T. Uthe

Inventor： Sarah D. Redpath ,  Randy A. Rendahl ,  Robert T. Uthe

IPC: G09G5/02

CPC classification number: G06T11/20

Abstract: A system and method for displaying objects in a plurality of layers. The layers are distinguished from one another using a variety of display attributes in order to emphasize objects in upper layers and de-emphasize objects in lower layers. The display attributes may include use of color (hue, saturation, and value), three dimensional images, fill patterns, and other display techniques. The user is able to change the layering in order to emphasize a different group, or category, of objects and de-emphasize other groups. The layers can be predefined, for example a hardware and software layers, or may be defined by analyzing the attributes corresponding with the objects. Objects and their attributes are stored in a data store, such as a relational database. Predefined layers include one or more of these attributes to use for matching.

Abstract translation: 一种用于在多个层中显示对象的系统和方法。 使用各种显示属性来区分这些层以便强调上层中的对象并且在较低层中去强调对象。 显示属性可以包括使用颜色（色相，饱和度和值），三维图像，填充图案和其他显示技术。 用户能够更改分层，以强调对象的不同组或类别，并强调其他组。 这些层可以是预定义的，例如硬件和软件层，或者可以通过分析与对象相对应的属性来定义。 对象及其属性存储在数据存储中，例如关系数据库。 预定义的层包含一个或多个这些属性用于匹配。

公开(公告)号：US07174386B2

公开(公告)日：2007-02-06

申请号：US10185697

申请日：2002-06-27

Applicant: James Brian Cunningham ,  Herman Dietrich Dierks, Jr. ,  Octavian Florin Herescu ,  Kiet Hien Lam

Inventor： James Brian Cunningham ,  Herman Dietrich Dierks, Jr. ,  Octavian Florin Herescu ,  Kiet Hien Lam

IPC: G06F15/16

CPC classification number: H04L69/16 ,  H04L1/1835 ,  H04L1/1854 ,  H04L69/163

Abstract: A system and method for tuning TCP/IP acknowledgments is provided. The system and method reduces the number of acknowledgments sent by a TCP/IP receiver by determining whether the connection state with the sender warrants using minimal acknowledgments. If minimal acknowledgments are used, the receiver sends fewer acknowledgments to the sender in response to received packets. The number of packets that are received before an acknowledgment is returned is increased until the delay value reaches a threshold value. The threshold value can be determined based on the size of the buffer setup to receive packets from the sender during the session. If errors, such as TCP/IP timeouts or duplicate packets, are detected, the threshold is changed to the last delay value that did not cause errors. If further errors are detected, the system is programmed to revert to sending traditional acknowledgments for the session.

Abstract translation: 提供了一种用于调整TCP / IP确认的系统和方法。 该系统和方法通过确定与发送方的连接状态是否使用最小确认来减少由TCP / IP接收器发送的确认的数量。 如果使用最小确认，则接收器响应于接收的分组向发送方发送较少的确认。 在返回确认之前接收的分组的数量增加，直到延迟值达到阈值。 可以基于在会话期间从发送方接收分组的缓冲器设置的大小来确定阈值。 如果检测到诸如TCP / IP超时或重复数据包之类的错误，则将阈值更改为不会导致错误的最后一个延迟值。 如果检测到进一步的错误，则系统被编程为恢复为会话发送传统确认。

公开(公告)号：US07146351B2

公开(公告)日：2006-12-05

申请号：US09996129

申请日：2001-11-28

Applicant: John William Sweitzer ,  Douglas Andrew Wood

Inventor： John William Sweitzer ,  Douglas Andrew Wood

IPC: G06F17/30

CPC classification number: G06F8/61 ,  Y10S707/99931 ,  Y10S707/99943

Abstract: Calibration factors determine how topograpy components are designed and built in order to support the management philosophies and methodologies. A marketing analysis may be used to identify the calibration factors that are needed to support a large market. In this manner, many calibration factors may be applied to a single topography requirement so that multiple operating environments and multiple management philosophies are supported by the topography. The components are stored in a component library and calibration factors corresponding to the components are stored in a data store. A customer's management philosophy, methodology, and operating environments are compared with the component metadata in order to identify suitable topography components which are installed on client computer systems to form to topography. Topography-neutral application components are adapted for installation on any topography regardless of the customer's management characteristics and operating environments.