公开(公告)号：US11152845B2

公开(公告)日：2021-10-19

申请号：US15970938

申请日：2018-05-04

Applicant: Microchip Technology Incorporated

Inventor： Gheorghe Turcan

IPC: H02M1/00 ,  H02M3/157 ,  H02M1/32 ,  H02M1/36

Abstract: An apparatus includes an input voltage, a comparator configured to generate a pulsed-width modulation signal based upon variation in the input voltage using a reference signal, and a switched mode power supply control circuit configured to control a power supply in voltage mode based at least upon the first pulsed-width modulation signal.

公开(公告)号：US11127660B2

公开(公告)日：2021-09-21

申请号：US16720220

申请日：2019-12-19

Applicant: Microchip Technology Incorporated

Inventor： Rangsun Kitnarong ,  Vichanart Nimibutr ,  Pattarapon Poolsup ,  Chanyuth Junjuewong

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31 ,  H05K1/18 ,  H01L21/56

Abstract: Methods are disclosed for forming flat no-leads packages (e.g., QFN packages) with soldering surfaces that are fully coated, e.g., by a tin immersion process, for improved solder connections of the packages to a PCB or other structure. The method includes forming a flat no-leads package structure including a leadframe terminal structure having an exposed top or bottom surface; forming a first coating of a first coating material (e.g., tin) on the exposed top or bottom surface; cutting through a full thickness of the leadframe terminal structure to define an exposed terminal sidewall surface; and forming a second coating of a second coating material (e.g., tin) over the full height of the exposed terminal sidewall surface. The coating (e.g., tin immersion coating) covering the full height of the leadframe terminal sidewall may enhance the flow of solder material, e.g., when soldering to a PCB, to provide an improved solder connection.

公开(公告)号：US20210281119A1

公开(公告)日：2021-09-09

申请号：US16863865

申请日：2020-04-30

Applicant: Microchip Technology Incorporated

Inventor： Santosh Bhandarkar ,  Alex Dumais

IPC: H02J50/60 ,  H02J50/12 ,  H02J50/40

Abstract: Object detection for wireless power transmitters and related systems, methods, and devices are disclosed. A controller for a wireless power transmitter is configured to receive a measurement voltage potential responsive to a tank circuit signal at a tank circuit, provide an alternating current (AC) signal to each of the plurality of transmit coils one at a time, and determine at least one of a resonant frequency and a quality factor (Q-factor) of the tank circuit responsive to each selected transmit coil of the plurality of transmit coils. The controller is also configured to select a transmit coil to use to transmit wireless power to a receive coil of a wireless power receiver responsive to the determined at least one of the resonant frequency and the Q-factor for each transmit coil of the plurality of transmit coils.

公开(公告)号：US20210272725A1

公开(公告)日：2021-09-02

申请号：US17071442

申请日：2020-10-15

Applicant: Microchip Technology Incorporated

Inventor： Paul Fest ,  Jacob Williams ,  Josh Kaufman

IPC: H01C17/00 ,  H01C7/00 ,  H01C17/30 ,  H01L27/06 ,  H01L49/02

Abstract: A method is provided for forming a thin film resistor (TFR) in an integrated circuit (IC) device. A TFR film is formed and annealed over an IC structure including IC elements and IC element contacts. At least one TFR cap layer is formed, and a TFR etch defines a TFR element from the TFR film. A TFR contact etch forms TFR contact openings over the TFR element, and a metal layer is formed over the IC structure and extending into the TFR contact openings to form metal contacts to the IC element contacts and the TFR element. The TFR cap layer(s), e.g., SiN cap and/or oxide cap formed over the TFR film, may (a) provide an etch stop during the TFR contact etch and/or (b) provide a hardmask during the TFR etch, which may eliminate the use of a photomask and thereby eliminate post-etch removal of photomask polymer.

公开(公告)号：US11101812B2

公开(公告)日：2021-08-24

申请号：US16731534

申请日：2019-12-31

Applicant: Microchip Technology Incorporated

Inventor： Ashish Senapati ,  Kevin Kilzer ,  Prashanth Pulipaka

IPC: H03M1/12

Abstract: Various embodiments relate to analog-to-digital converter (ADC) controllers. An ADC controller may include a number of contexts configured for coupling to an ADC, wherein each context having at least one register for storing at least one configurable parameter. The ADC controller may also include a sequencer operatively coupled to the number of contexts and configured to perform a programmed conversion sequence based on one or more configurable parameters of one or more contexts of the number of contexts. Methods of performing an analog-to-digital (A/D) conversion sequence, and methods of configuring a number of contexts for an analog-to-digital converter (ADC) controller, are also disclosed.

公开(公告)号：US20210258043A1

公开(公告)日：2021-08-19

申请号：US17037919

申请日：2020-09-30

Applicant: Microchip Technology Incorporated

Inventor： Marco Rohleder ,  Stefan Weiers

IPC: H04B3/54 ,  H02J7/00 ,  H03K17/687 ,  A24F40/90 ,  A24F40/65

Abstract: A system for transmitting power and data through a two pin connection interface may have a first device having a power source, a first microcontroller with a first communication peripheral coupled with a first pin and a first control port coupled with a gate of a first MOSFET whose switch path couples the power source with the first pin; and a second device having a battery, a second microcontroller with a second communication peripheral coupled with a first pin and a second control port coupled with a gate of a second MOSFET whose switch path couples the battery with the first pin of the second device. When the devices are coupled, the MOSFETs are synchronously turned on and off, wherein during an off-cycle a data transfer between the first and second device takes place through the first and second communication peripherals of the first and second device, respectively.

公开(公告)号：US11088666B2

公开(公告)日：2021-08-10

申请号：US16411449

申请日：2019-05-14

Applicant: Microchip Technology Incorporated

Inventor： Keith Edwin Curtis ,  Ward Brown ,  John Charais ,  Steve Kennelly ,  Dave Suda ,  Huamin Zhou ,  Clark Rogers ,  Mudit Gupta

IPC: H03F3/45

Abstract: An operational amplifier with totem pole connected output transistors having inputs coupled to multiplexers for selectable coupling of signals and voltage levels thereto. The high and low output transistors may be forced hard on or hard off in addition to normal coupling of signals thereto. The operation of the output transistors may be dynamically changed to pass only positive going signals, negative going signals, placed in a tristate high impedance state, hard connected to a supply voltage and/or hard connected to supply common return. A core independent peripheral (CIP) may also be coupled to the operational amplifier for dynamically changing the multiplexer inputs in real time, as can external control signals to a control circuit coupled to the multiplexers.

公开(公告)号：US11088024B2

公开(公告)日：2021-08-10

申请号：US16450391

申请日：2019-06-24

Applicant: Microchip Technology Incorporated

Inventor： Paul Fest

IPC: H01L21/768 ,  H01L21/311 ,  H01L49/02

Abstract: A method is provided for forming a thin film resistor (TFR) in an integrated circuit (IC) including IC elements, e.g., memory components. A first contact etch stop layer is formed over the IC elements. A TFR layer stack including a TFR etch stop layer, a TFR film layer, and a second contact etch stop layer is formed over the first contact etch stop layer, and in some cases over one or more pre-metal dielectric layers. A patterned mask is formed over the IC stack, and the stack is etched, through both the first and second contact etch stop layers, to simultaneously form (a) first contact openings exposing contact regions of the IC elements and (b) second contact opening(s) exposing the TFR film layer. The first and second contact openings are filled with conductive material to form conductive contacts to the IC elements and the TFR film layer.

公开(公告)号：US11074209B2

公开(公告)日：2021-07-27

申请号：US16588562

申请日：2019-09-30

Applicant: Microchip Technology Incorporated

Inventor： Hongming An ,  James Ho ,  Congqing Xiong ,  Henry Liang ,  John Junling Zang

IPC: G06F13/40 ,  G06F1/10 ,  G06F9/4401 ,  G06F9/30

Abstract: Circuitry of a physical layer for interfacing with a communication bus of a wired local area network is disclosed. The circuitry includes a variable delay driver operably coupled to a communication bus. The communication bus includes a shared transmission medium. The variable delay driver is configured to control a slew rate of a driven transmit signal at the driver output. The circuitry also includes receiver circuitry operably coupled to the communication bus. The circuitry further includes a common mode dimmer operably coupled to the receiver circuitry and the communication bus. The common mode dimmer is configured to protect the receiver circuitry from common mode interference.

公开(公告)号：US11043471B2

公开(公告)日：2021-06-22

申请号：US16540117

申请日：2019-08-14

Applicant: Microchip Technology Incorporated

Inventor： Justin Sato ,  Bomy Chen

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/13 ,  H01L21/48 ,  H01L25/00 ,  H01L23/498

Abstract: A mixed-orientation multi-die (“MOMD”) integrated circuit package includes dies mounted in different physical orientations. An MOMD package includes both (a) one or more dies horizontally-mounted dies (HMDs) mounted horizontally to a horizontally-extending die mount base and (b) one or more vertically-mounted dies (VMDs) mounted vertically to the horizontally-extending die mount base. HMDs may include FPGAs or other high performance chips, while VMDs may include low performance chips and other physical structures such as heat dissipators, memory, high voltage/analog devices, sensors, or MEMS, for example. The die mount base of an MOMD package may include structures for aligning and mounting VMD(s), for example, VMD slots for receiving each mounted VMD, and VMD alignment structures that facilitate aligning and/or guiding a vertical mounting of each VMD to the die mount base. MOMD packages may provide a reduced lateral footprint and increased die integration per unit area, as compared with conventional multi-die packages.