公开(公告)号：US20200211935A1

公开(公告)日：2020-07-02

申请号：US16720220

申请日：2019-12-19

Applicant: Microchip Technology Incorporated

Inventor： Rangsun Kitnarong ,  Vichanart Nimibutr ,  Pattarapon Poolsup ,  Chanyuth Junjuewong

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/78 ,  H05K1/18 ,  H01L23/31 ,  H01L23/00

Abstract: Methods are disclosed for forming flat no-leads packages (e.g., QFN packages) with soldering surfaces that are fully coated, e.g., by a tin immersion process, for improved solder connections of the packages to a PCB or other structure. The method includes forming a flat no-leads package structure including a leadframe terminal structure having an exposed top or bottom surface; forming a first coating of a first coating material (e.g., tin) on the exposed top or bottom surface; cutting through a full thickness of the leadframe terminal structure to define an exposed terminal sidewall surface; and forming a second coating of a second coating material (e.g., tin) over the full height of the exposed terminal sidewall surface. The coating (e.g., tin immersion coating) covering the full height of the leadframe terminal sidewall may enhance the flow of solder material, e.g., when soldering to a PCB, to provide an improved solder connection.

公开(公告)号：US20170294367A1

公开(公告)日：2017-10-12

申请号：US15480661

申请日：2017-04-06

Applicant: Microchip Technology Incorporated

Inventor： Rangsun Kitnarong ,  Prachit Punyapor ,  Pattarapon Poolsup ,  Swat Kumsai

IPC: H01L23/495 ,  H01L21/56 ,  H05K3/34 ,  H01L21/78 ,  H01L21/66 ,  H01L23/00 ,  H01L21/288

CPC classification number: H01L23/4952 ,  H01L21/288 ,  H01L21/4835 ,  H01L21/561 ,  H01L21/78 ,  H01L22/14 ,  H01L23/3107 ,  H01L23/49541 ,  H01L23/49582 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L2223/544 ,  H01L2223/54433 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/4847 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/81192 ,  H01L2224/85207 ,  H01L2224/92227 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/14 ,  H01L2924/17747 ,  H01L2924/181 ,  H01L2924/3511 ,  H05K3/3442 ,  H05K3/3494 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00

Abstract: According to an embodiment of the present disclosure, a method for manufacturing an integrated circuit (IC) device may include mounting an IC chip onto a center support structure of a leadframe. The leadframe may include: a plurality of pins extending from the center support structure; a groove running perpendicular to the individual pins of the plurality of pins around the center support structure; and a bar connecting the plurality of pins remote from the center support structure. The method may further include: bonding the IC chip to at least some of the plurality of pins; encapsulating the leadframe and bonded IC chip, including filling the groove with encapsulation compound; removing the encapsulation compound from the groove, thereby exposing at least a portion of the individual pins of the plurality of pins; plating the exposed portion of the plurality of pins; and cutting the IC package free from the bar by sawing through the encapsulated lead frame along the groove using a first saw width less than a width of the groove.

公开(公告)号：US20190221502A1

公开(公告)日：2019-07-18

申请号：US15939586

申请日：2018-03-29

Applicant: Microchip Technology Incorporated

Inventor： Joseph Fernandez ,  Rangsun Kitnarong ,  Tarapong Soontornvipart ,  Janwit Apirukaramwong ,  Prachit Punyapor ,  Supakrits Suttiwat ,  Ekgachai Kenganantanon

IPC: H01L23/495

CPC classification number: H01L23/4952 ,  H01L23/49503 ,  H01L23/49575

Abstract: An apparatus includes a lead frame paddle configured for mounting a semiconductor die. The apparatus further includes a plating area formed on the lead frame paddle. The plating area is configured to receive a down bond from a semiconductor die placed on the lead frame paddle. The apparatus further includes an exposed gap between an outer edge of the plating area and an outer edge of the lead frame paddle.

公开(公告)号：US20160148877A1

公开(公告)日：2016-05-26

申请号：US14946024

申请日：2015-11-19

Applicant: MICROCHIP TECHNOLOGY INCORPORATED

Inventor： Rangsun Kitnarong ,  Prachit Punyapor ,  Watcharapong Nokdee

IPC: H01L23/544 ,  H01L21/48 ,  H01L21/66 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L23/544 ,  H01L21/4839 ,  H01L21/4842 ,  H01L21/4889 ,  H01L22/12 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49582 ,  H01L23/49838 ,  H01L2223/5446 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: According to an embodiment of the present disclosure, a method for manufacturing an integrated circuit (IC) device may include mounting an IC chip onto a center support structure of a leadframe, bonding the IC chip to at least some of the plurality of pins, encapsulating the leadframe and bonded IC chip, sawing a step cut into the encapsulated leadframe, plating the exposed portion of the plurality of pins, and cutting the IC package free from the bar. The leadframe may include a plurality of pins extending from the center support structure and a bar connecting the plurality of pins remote from the center support structure. The step cut may be sawn into the encapsulated leadframe along a set of cutting lines using a first saw width without separating the bonded IC package from the bar, thereby exposing at least a portion of the plurality of pins. The IC package may be cut free from the bar by sawing through the encapsulated lead frame at the set of cutting lines using a second saw width less than the first saw width.

Abstract translation: 根据本公开的实施例，用于制造集成电路（IC）器件的方法可以包括将IC芯片安装到引线框的中心支撑结构上，将IC芯片连接到多个引脚中的至少一些，封装 引线框架和粘合IC芯片，锯切封装的引线框架的步骤，电镀多个引脚的暴露部分，以及切割没有棒的IC封装。 引线框架可以包括从中心支撑结构延伸的多个销和连接远离中心支撑结构的多个销的杆。 可以沿着一组切割线使用第一锯宽度将步进切割锯切成封装的引线框架，而不将结合的IC封装与条分离，从而暴露多个引脚的至少一部分。 通过使用小于第一锯宽度的第二锯宽度，通过在所述一组切割线处锯切通过所述封装的引线框架，可以切割所述IC封装。

公开(公告)号：US11887864B2

公开(公告)日：2024-01-30

申请号：US17326488

申请日：2021-05-21

Applicant: Microchip Technology Incorporated

Inventor： Wichai Kovitsophon ,  Rangsun Kitnarong ,  Ekgachai Kenganantanon ,  Pattarapon Poolsup ,  Watcharapong Nokde ,  Chanyuth Junjuewong

IPC: H01L21/56 ,  H01L21/78 ,  H01L23/544 ,  H01L21/48 ,  H01L21/60

CPC classification number: H01L21/56 ,  H01L21/4839 ,  H01L21/78 ,  H01L23/544 ,  H01L2021/60007

Abstract: Flat no-leads integrated circuit (IC) packages are formed with solder wettable leadframe terminals. Dies are mounted on die attach pads, bonded to adjacent leadframe terminal structures, and encapsulated in a mold compound. A laser grooving process removes mold compound from a leadframe terminal groove extending along a row of leadframe terminal structures. A saw step cut along the leadframe terminal groove extends partially through the leadframe thickness to define a saw step cut groove. Exposed leadframe surfaces, including surfaces exposed by the saw step cut, are plated with a solder-enhancing material. A singulation cut is performed along the saw step cut groove to define leadframe terminals with end surfaces plated with the solder-enhancing material. The laser grooving process may improve the results of the saw step cut, and the saw step cut may remove mold compound not removed by the laser grooving process.

公开(公告)号：US11127660B2

公开(公告)日：2021-09-21

申请号：US16720220

申请日：2019-12-19

Applicant: Microchip Technology Incorporated

Inventor： Rangsun Kitnarong ,  Vichanart Nimibutr ,  Pattarapon Poolsup ,  Chanyuth Junjuewong

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31 ,  H05K1/18 ,  H01L21/56

Abstract: Methods are disclosed for forming flat no-leads packages (e.g., QFN packages) with soldering surfaces that are fully coated, e.g., by a tin immersion process, for improved solder connections of the packages to a PCB or other structure. The method includes forming a flat no-leads package structure including a leadframe terminal structure having an exposed top or bottom surface; forming a first coating of a first coating material (e.g., tin) on the exposed top or bottom surface; cutting through a full thickness of the leadframe terminal structure to define an exposed terminal sidewall surface; and forming a second coating of a second coating material (e.g., tin) over the full height of the exposed terminal sidewall surface. The coating (e.g., tin immersion coating) covering the full height of the leadframe terminal sidewall may enhance the flow of solder material, e.g., when soldering to a PCB, to provide an improved solder connection.

公开(公告)号：US20200211936A1

公开(公告)日：2020-07-02

申请号：US16720269

申请日：2019-12-19

Applicant: Microchip Technology Incorporated

Inventor： Rangsun Kitnarong ,  Vichanart Nimibutr ,  Pattarapon Poolsup ,  Chanyuth Junjuewong

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/78 ,  H01L23/00 ,  H05K1/18 ,  H01L23/31

Abstract: Methods are disclosed for forming flat leads packages (e.g., QFP or SOT packages) having leads coated with a solder-enhancing material for improved solder mounting to a PCB or other structure. The method may include forming a flat leads package structure including an array of encapsulated IC structures formed on a common leadframe. An isolation cutting process may be performed to electrically isolate the IC structures from each other and define a plurality of leadframe leads extending from each IC structure. After the isolation cutting process, an immersion coating process is performed to coat exposed surfaces of the leadframe leads, including the full surface area of a distal end of each leadframe lead. The coating (e.g., tin coating) covering the distal ends of the leadframe leads may enhance the flow of solder material, e.g., when soldering to a PCB, to provide an improved solder connection.

公开(公告)号：US11101200B2

公开(公告)日：2021-08-24

申请号：US16720269

申请日：2019-12-19

Applicant: Microchip Technology Incorporated

Inventor： Rangsun Kitnarong ,  Vichanart Nimibutr ,  Pattarapon Poolsup ,  Chanyuth Junjuewong

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31 ,  H05K1/18 ,  H01L21/56

Abstract: Methods are disclosed for forming flat leads packages (e.g., QFP or SOT packages) having leads coated with a solder-enhancing material for improved solder mounting to a PCB or other structure. The method may include forming a flat leads package structure including an array of encapsulated IC structures formed on a common leadframe. An isolation cutting process may be performed to electrically isolate the IC structures from each other and define a plurality of leadframe leads extending from each IC structure. After the isolation cutting process, an immersion coating process is performed to coat exposed surfaces of the leadframe leads, including the full surface area of a distal end of each leadframe lead. The coating (e.g., tin coating) covering the distal ends of the leadframe leads may enhance the flow of solder material, e.g., when soldering to a PCB, to provide an improved solder connection.

公开(公告)号：US20170005030A1

公开(公告)日：2017-01-05

申请号：US15263030

申请日：2016-09-12

Applicant: Microchip Technology Incorporated

Inventor： Rangsun Kitnarong ,  Prachit Punyapor ,  Ekgachai Kenganantanon

IPC: H01L23/495 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31 ,  H01L21/66 ,  H01L21/288 ,  H05K3/34 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/49541 ,  H01L21/288 ,  H01L21/4825 ,  H01L21/4839 ,  H01L21/4842 ,  H01L21/4889 ,  H01L21/56 ,  H01L21/561 ,  H01L21/78 ,  H01L22/14 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49548 ,  H01L23/544 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L2223/54453 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/181 ,  H05K3/3442 ,  H05K3/3494 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099

Abstract: According to an embodiment of the present disclosure, a leadframe for an integrated circuit (IC) device may comprise a center support structure for mounting an IC chip, a plurality of pins extending from the center support structure, and a bar connecting the plurality of pins remote from the center support structure. Each pin of the plurality of pins may include a dimple.

Abstract translation: 根据本公开的实施例，用于集成电路（IC）装置的引线框架可以包括用于安装IC芯片的中心支撑结构，从中心支撑结构延伸的多个销以及连接多个销 远离中心支撑结构。 多个销的每个销可以包括凹坑。

公开(公告)号：US20160148876A1

公开(公告)日：2016-05-26

申请号：US14945679

申请日：2015-11-19

Applicant: MICROCHIP TECHNOLOGY INCORPORATED

Inventor： Rangsun Kitnarong ,  Prachit Punyapor ,  Ekgachai Kenganantanon

IPC: H01L23/544 ,  H01L23/31 ,  H01L21/56 ,  H01L23/495 ,  H01L21/66 ,  H01L21/48

CPC classification number: H01L23/49541 ,  H01L21/288 ,  H01L21/4825 ,  H01L21/4839 ,  H01L21/4842 ,  H01L21/4889 ,  H01L21/56 ,  H01L21/561 ,  H01L21/78 ,  H01L22/14 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49548 ,  H01L23/544 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L2223/54453 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/181 ,  H05K3/3442 ,  H05K3/3494 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099

Abstract: According to an embodiment of the present disclosure, a leadframe for an integrated circuit (IC) device may comprise a center support structure for mounting an IC chip, a plurality of pins extending from the center support structure, and a bar connecting the plurality of pins remote from the center support structure. Each pin of the plurality of pins may include a dimple.

Abstract translation: 根据本公开的实施例，用于集成电路（IC）装置的引线框架可以包括用于安装IC芯片的中心支撑结构，从中心支撑结构延伸的多个销以及连接多个销 远离中心支撑结构。 多个销的每个销可以包括凹坑。