公开(公告)号：US20140300335A1

公开(公告)日：2014-10-09

申请号：US14353991

申请日：2012-09-25

Applicant: ST-Ericsson SA

Inventor： Benoit Labbe ,  David Chesneau

IPC: H02M3/158

CPC classification number: H02M3/158 ,  H02M3/156

Abstract: A circuit with current-controlled frequency implements a node (2) with an electrical charge which alternatively increases and decreases between two thresholds. The slew rate of the node can be adjusted using a tunable current source (1), thereby enabling tuning of a switching delay. The circuit may be used for controlling the switching frequency of a switch-mode power supply.

Abstract translation: 具有电流控制频率的电路实现具有在两个阈值之间可选地增加和减少的电荷的节点（2）。 可以使用可调电流源（1）来调整节点的转换速率，从而实现对开关延迟的调节。 该电路可用于控制开关模式电源的开关频率。

公开(公告)号：US20140258765A1

公开(公告)日：2014-09-11

申请号：US13784909

申请日：2013-03-05

Applicant: ST-ERICSSON SA

Inventor： Håkan Persson

IPC: G06F1/06

CPC classification number: G06F1/06 ,  G06F1/10 ,  G06F1/3203 ,  G06F1/3243 ,  Y02D10/152

Abstract: High frequency current transients, due to logic switching inside the CPU, are reduced by applying clock signals having different relative phases to different parts of the CPU. This reduces the amplitude of current variations, and hence noise induced onto the power supply voltage. In some embodiments, different CPU cores within multi-core CPUs are clocked with a different clock phases. Additionally a method and circuit for low-latency communication in the presence of large OCV effects is provided. The low-latency communication may be based on a FIFO. Strobes are used to indicate safe points in time to update and read signals between transmitter and receiver. The strobes are generated in a central clock generation module. The strobe mechanism is used to transfer the read and write pointers between the transmitter and receiver, while the payload data is transferred using a FIFO data array that allows data writes to be asynchronous to corresponding data reads.

Abstract translation: 通过将具有不同相对相位的时钟信号施加到CPU的不同部分，由于CPU内部的逻辑切换引起的高频电流瞬变被减少。 这降低了电流变化的幅度，并因此降低了对电源电压的感应。 在一些实施例中，多核CPU内的不同CPU内核以不同的时钟相位计时。 另外，提供了在存在大的OCV效应的情况下用于低等待时间通信的方法和电路。 低延迟通信可以基于FIFO。 标记用于指示安全点在更新和读取发射机和接收机之间的信号。 选通在中央时钟发生模块中产生。 选通机制用于在发送器和接收器之间传送读取和写入指针，同时使用允许数据写入与相应数据读取异步的FIFO数据数据传输有效载荷数据。

公开(公告)号：US20140256274A1

公开(公告)日：2014-09-11

申请号：US14353655

申请日：2012-10-17

Applicant: ST-Ericsson SA

Inventor： Vincent Knopik

IPC: H04B1/44

CPC classification number: H04B1/44 ,  H04B1/0458 ,  H04B1/406

Abstract: There is described a RF front end circuit comprising: a common impedance matching network (4) connected to an output terminal (5), a first power amplifier (1), PA, arranged to drive power to the output terminal through the common impedance matching network, a second PA (2) adapted to drive power to the output terminal through the common impedance matching network and a second impedance matching network (12), a reference terminal (9, 92) at a reference voltage (Vdd2), the second impedance matching network comprising at least a first connection path to the reference terminal, a second connection path to the second PA and a third connection path to the common impedance matching network, wherein, the second impedance matching network comprises a first impedance switch (SI1) configured to open the first connection path responsive to the second PA being put into an OFF state.

Abstract translation: 描述了一种RF前端电路，包括：连接到输出端子（5）的公共阻抗匹配网络（4），第一功率放大器（1），PA，布置成通过公共阻抗匹配来向输出端子驱动电力 网络，适于通过公共阻抗匹配网络向第二输出端子驱动电力的第二PA（2）和第二阻抗匹配网络（12），参考电压（Vdd2）的参考端子（9,92），第二阻抗匹配网络 阻抗匹配网络，包括至少到参考终端的第一连接路径，到第二PA的第二连接路径和到公共阻抗匹配网络的第三连接路径，其中，第二阻抗匹配网络包括第一阻抗开关（SI1） 被配置为响应于所述第二PA被置于OFF状态来打开所述第一连接路径。

公开(公告)号：US20140250290A1

公开(公告)日：2014-09-04

申请号：US13781852

申请日：2013-03-01

Applicant: ST-ERICSSON SA

Inventor： Per Ståhl ,  Håkan Englund ,  Hans Holmberg

IPC: G06F9/44

CPC classification number: G06F9/4401 ,  G06F21/575 ,  H04L9/0897 ,  H04L9/3247

Abstract: A temporary anti-rollback table—which is cryptographically signed, unique to a specific device, and includes a version number—is provided to an electronic device requiring a replacement anti-rollback table. The table is verified by the device, and loaded to memory following a reboot. The memory image of the table is used to perform anti-rollback verification of all trusted software components as they are loaded. After booting, the memory image of the table is written in a secure manner to non-volatile memory as a replacement anti-rollback table, and the temporary anti-rollback table is deleted. The minimum required table version number in OTP memory is incremented. The temporary anti-rollback table is created and signed using a private key at authorized service centers; a corresponding public key in the electronic device verifies its authenticity.

Abstract translation: 向需要更换防折返表的电子设备提供临时防折返表，该表被加密地签名，并且包括特定设备，并且包括版本号。 该表由设备验证，并在重新启动后加载到内存。 表的内存映像用于在所有受信任的软件组件加载时对所有受信任的软件组件进行反卷回验证。 引导后，表的内存映像以安全的方式写入非易失性存储器作为替换的反滚动表，并且删除了临时防回滚表。 OTP内存中最小的所需表版本号增加。 在授权服务中心使用私钥创建和签名临时防折返表; 电子设备中的相应公钥验证其真实性。

公开(公告)号：US20140247073A1

公开(公告)日：2014-09-04

申请号：US14240571

申请日：2012-09-27

Applicant: ST-Ericsson SA

Inventor： Fabien Journet

IPC: H03K21/08

CPC classification number: H03K21/08 ,  H04B15/06

Abstract: The invention concerns a device for providing a spread frequency clock signal, comprising: -an input (51) to receive a first clock signal having a first frequency; -a programmable clock divider (52) to generate the spread frequency clock signal from the first clock signal; -a first Feedback Shift Register (21), FSR, comprising at least one stage, the FSR being adapted to generate any of an odd number M of different values, the FSR being adapted to pseudo-randomly generate a first sequence of first output values, each corresponding to one of said M different values, and to provide a first output value, according to the sequence, during each clock cycle of the spread frequency clock signal; -a control unit (22) adapted to select a division factor of the programmable clock divider based on the first output value of the FSR during each clock cycle of the spread frequency clock signal; -an output (53) for providing the spread frequency clock signal.

Abstract translation: 本发明涉及一种用于提供扩展频率时钟信号的装置，包括： - 输入（51），用于接收具有第一频率的第一时钟信号; - 可编程时钟分频器（52），用于从所述第一时钟信号产生所述扩频时钟信号; - 第一反馈移位寄存器（21），FSR，包括至少一级，所述FSR适于生成不同值的奇数M中的任何一个，所述FSR适于伪随机生成第一输出值的第一序列 ，每个对应于所述M个不同值中的一个，并且在扩展频率时钟信号的每个时钟周期期间根据该序列提供第一输出值; - 控制单元（22），适于在扩展频率时钟信号的每个时钟周期期间基于FSR的第一输出值选择可编程时钟分频器的分频系数; - 用于提供扩频时钟信号的输出（53）。

公开(公告)号：US08797069B2

公开(公告)日：2014-08-05

申请号：US13910366

申请日：2013-06-05

Applicant: ST-Ericsson SA

Inventor： Leonardus Hesen ,  Paul Mateman ,  Johannes Petrus Antonius Frambach

IPC: H03K21/00

CPC classification number: H03K21/00 ,  H03K21/026 ,  H03K21/12

Abstract: High-speed RF differential, Quadrature, divide-by-2 clock divider designs are based on inverters and clocking circuits connected in a serial ring formation. In one embodiment, only NMOS transistors are used in the inverters, and only PMOS transistors are used in the clocking circuits. This structure uses only 12 transistors. The input can be coupled directly to a VCO output, and provides minimum loading, as each VCO output is connected to only two transistors. Another embodiment comprises clocked inverter stages connected in a serial ring configuration with inverters between stages. The RF clock (or VCO signal) is used at the outer side of the inverters for speed improvement. In both circuits, positive and negative clock inputs are connected alternately at each stage of the ring.

Abstract translation: 高速RF差分，正交，2分频时钟分频器设计基于以串联环形形式连接的逆变器和时钟电路。 在一个实施例中，在反相器中仅使用NMOS晶体管，并且在时钟电路中仅使用PMOS晶体管。 该结构仅使用12个晶体管。 由于每个VCO输出仅连接到两个晶体管，输入可以直接耦合到VCO输出，并提供最小的负载。 另一个实施例包括以串联环形连接的时钟反相级，在级之间具有反相器。 逆变器外侧使用RF时钟（或VCO信号）进行速度改进。 在两个电路中，正和负时钟输入在环的每个阶段交替连接。

公开(公告)号：US08787325B2

公开(公告)日：2014-07-22

申请号：US13622762

申请日：2012-09-19

Applicant: ST-Ericsson SA

Inventor： Jorgen Van Parys

IPC: H04J3/00 ,  H04W4/00 ,  H04L12/26

CPC classification number: H04W72/12 ,  H04W28/021 ,  H04W28/10 ,  H04W72/1242

Abstract: Time frames (TFs) are allocated for performance of transactions of a low latency data stream (LLDS) and a best effort data stream (BEDS) in Bluetooth®-like equipment, wherein payload carrying packets of the different data streams are equal in size, each occupying multiple TFs. An overrule mechanism enables uncompleted transactions of one data stream to continue as needed into TFs allocated to another data stream. Every TF within an allocation window (AW) is individually allocated to the LLDS or the BEDS, and plural TFs immediately following the AW form a guard space between adjacent AWs, the guard space being allocated to neither the LLDDS or the BEDS. Configuration of the AW and of the guard space guarantees the LLDS a first opportunity to transmit a payload carrying packet and continued opportunities to retransmit the packet until successful, after which the BEDS is given an opportunity for transmission and possible retransmissions.

Abstract translation: 时分帧（TF）被分配用于在蓝牙类设备中执行低延迟数据流（LLDS）和尽力数据流（BEDS）的事务，其中负载不同数据流的分组的负载的大小相等， 每个占用多个TF。 重叠机制使一个数据流的未完成事务可以根据需要继续分配给另一个数据流的TF。 分配窗口（AW）内的每个TF单独分配给LLDS或BEDS，并且AW之后的多个TF形成相邻AW之间的保护空间，保护空间既不分配给LLDDS也不分配给BEDS。 AW和保护空间的配置保证了LLDS第一次发送携带有效载荷的有效载荷的机会，并继续重新发送数据包的机会，直到成功，然后给予BEDS传输机会和可能的重传。

公开(公告)号：US20140184328A1

公开(公告)日：2014-07-03

申请号：US14136469

申请日：2013-12-20

Applicant: ST-Ericsson SA

Inventor： Vincent BINET ,  Emmanuel ALLIER ,  Francois AMIARD

IPC: H03F3/217

CPC classification number: H03F3/2171 ,  H03F1/0277 ,  H03F3/2173 ,  H03F3/72 ,  H03F2203/7206 ,  H03F2203/7236

Abstract: There is disclosed a driver circuit for a power amplifier of class D type having a segmented architecture with at least one current branch which can be powered down in a low power mode of operation of the circuit. The branch comprising a switch with a cascode MOS transistor, the circuit further comprises a bias circuitry adapted for dynamically generating a dynamic bias control signal so as to cause the cascode MOS transistor of the switch to be ‘Off’ in the low power mode.

Abstract translation: 公开了一种用于D类功率放大器的驱动电路，该驱动电路具有分段结构，具有至少一个电流分支，该电流分支可在该电路的低功率工作模式下掉电。 所述分支包括具有共源共栅MOS晶体管的开关，所述电路还包括偏置电路，所述偏置电路适于动态产生动态偏置控制信号，以使所述开关的共源共栅MOS晶体管处于低功率模式中的“关”。

公开(公告)号：US08767876B2

公开(公告)日：2014-07-01

申请号：US13721455

申请日：2012-12-20

Applicant: ST-Ericsson SA

Inventor： Jorma Pertti Matero

IPC: H04L27/12

CPC classification number: H04L27/00 ,  H03C3/0933 ,  H03C2200/0016 ,  H03C2200/002 ,  H03C2200/0054 ,  H04L25/03834 ,  H04L25/06 ,  H04L27/2017 ,  H04L27/367

Abstract: Problems arising from a pre-emphasis filter, particularly an infinite-impulse-response filter, in a signal modulator are solved by detecting sequences of the same bit or symbol in a modulation signal and compensating the corresponding d.c. offset in the signal generated by the pre-emphasis filter without real-time feedback. The amount of offset compensation can be defined during design of the modulator or adjusted or calibrated during production. It is not necessary to change the transfer function of the pre-emphasis filter, but only to correct the d.c. offset of the filter output signal.

Abstract translation: 通过检测调制信号中相同位或符号的序列来解决信号调制器中的预加重滤波器，特别是无限脉冲响应滤波器引起的问题，并补偿相应的直流电平。 由预加重滤波器产生的信号中的偏移量没有实时反馈。 偏移补偿量可以在调制器的设计期间进行定义，或者在生产期间进行调整或校准。 不需要改变预加重滤波器的传递函数，只能改正直流电压。 滤波器输出信号的偏移。

公开(公告)号：US20140139046A1

公开(公告)日：2014-05-22

申请号：US13995365

申请日：2012-02-09

Applicant: ST-ERICSSON SA

Inventor： Gajendranath Chowdary ,  Ravpreet Singh ,  Shyam Somayajula

IPC: H04R3/00 ,  H02J7/00

CPC classification number: H04R3/00 ,  H02J7/0042 ,  H02J7/0055 ,  H04R2410/00 ,  Y10T307/858

Abstract: An electrical interface circuit is disclosed. The circuit comprises a microphone circuit (100); a battery charger circuit (200); and an electrical connector (300) for connecting said electrical interface circuit to an external device. The electrical connector has a pin (302) on which signals are multiplexed for connecting either the battery charger circuit to an external supply voltage or the microphone circuit to an external microphone. The battery charger circuit comprises an amplifying circuit (202) for controlling voltage or current to a battery (400) at battery charging and a p-type power transistor. The pin is connected to the microphone circuit and to a source of the p-type power transistor, and when a voltage applied to the pin exceeds the battery voltage, the p-type power transistor will provide current from the pin to the charger circuit, and otherwise the charger circuit and battery is disconnected from the pin. A method of multiplexing signals on the electrical interface circuit is also disclosed.

Abstract translation: 公开了一种电接口电路。 该电路包括麦克风电路（100）; 电池充电器电路（200）; 以及用于将所述电接口电路连接到外部设备的电连接器（300）。 电连接器具有引脚（302），信号被多路复用以将电池充电器电路连接到外部电源电压或麦克风电路连接到外部麦克风。 电池充电器电路包括用于在电池充电期间控制电池（400）的电压或电流的放大电路（202）和p型功率晶体管。 引脚连接到麦克风电路和p型功率晶体管的源极，并且当施加到引脚的电压超过电池电压时，p型功率晶体管将从引脚向充电器电路提供电流， 否则充电器电路和电池与引脚断开连接。 还公开了一种在电接口电路上复用信号的方法。