公开(公告)号：US20170046272A1

公开(公告)日：2017-02-16

申请号：US15133033

申请日：2016-04-19

Applicant: Advanced Micro Devices, Inc.

Inventor： Amin Farmahini-Farahani ,  David A. Roberts

IPC: G06F12/10 ,  G06F3/06 ,  G06F12/14

CPC classification number: G06F12/1009 ,  G06F3/0604 ,  G06F3/0616 ,  G06F3/0644 ,  G06F3/0665 ,  G06F3/0683 ,  G06F12/0238 ,  G06F12/1408 ,  G06F12/1441 ,  G06F2212/1016 ,  G06F2212/1052 ,  G06F2212/205 ,  G06F2212/401 ,  G06F2212/402 ,  G06F2212/7201 ,  G06F2212/7211

Abstract: Systems, apparatuses, and methods for implementing logical memory address regions in a computing system. The physical memory address space of a computing system may be partitioned into a plurality of logical memory address regions. Each logical memory address region may be dynamically configured at run-time to meet changing application needs of the system. Each logical memory address region may also be configured separately from the other logical memory address regions. Each logical memory address region may have associated parameters that identify region start address, region size, cell-level mode, physical-to-device mapping scheme, address masks, access permissions, wear-leveling data, encryption settings, and compression settings. These parameters may be stored in a table which may be used when processing memory access requests.

Abstract translation: 用于在计算系统中实现逻辑存储器地址区域的系统，装置和方法。 计算系统的物理存储器地址空间可以被划分成多个逻辑存储器地址区域。 每个逻辑存储器地址区域可以在运行时动态配置以满足系统的不断变化的应用需求。 每个逻辑存储器地址区域也可以与其他逻辑存储器地址区域分开配置。 每个逻辑存储器地址区域可以具有标识区域起始地址，区域大小，小区级模式，物理到设备映射方案，地址掩码，访问权限，损耗均衡数据，加密设置和压缩设置的相关参数。 这些参数可以存储在处理存储器访问请求时可以使用的表中。

公开(公告)号：US20160371014A1

公开(公告)日：2016-12-22

申请号：US14743091

申请日：2015-06-18

Applicant: Advanced Micro Devices, Inc.

Inventor： David A. Roberts

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0659 ,  G06F3/0673 ,  G06F3/0679 ,  G06F3/0688

Abstract: The disclosed embodiments provide a system for processing a memory command on a computer system. During operation, a command scheduler executing on a memory controller of the computer system obtains a predicted latency of the memory command based on a memory address to be accessed by the memory command. Next, the command scheduler orders the memory command with other memory commands in a command queue for subsequent processing by a memory resource on the computer system based on the predicted latency of the memory command.

Abstract translation: 所公开的实施例提供了一种用于处理计算机系统上的存储器命令的系统。 在操作期间，在计算机系统的存储器控​​制器上执行的命令调度器基于由存储器命令访问的存储器地址获得存储器命令的预测等待时间。 接下来，命令调度器根据预测的存储器命令的等待时间，通过命令队列中的其他存储器命令对计算机系统上的存储器资源进行后续处理。

公开(公告)号：US20160155491A1

公开(公告)日：2016-06-02

申请号：US14555639

申请日：2014-11-27

Applicant: Advanced Micro Devices, Inc.

Inventor： David A. Roberts ,  Michael Ignatowski

IPC: G11C11/406

CPC classification number: G11C11/40607 ,  G11C11/40611 ,  G11C11/40615 ,  G11C11/40626 ,  G11C2211/4067 ,  G11C2211/4068

Abstract: A memory retention controller may include a data structure configured to store a memory refresh interval corresponding to a memory region in a memory subsystem and control logic coupled with the data structure. The control logic is configured to perform a first refresh of the memory region prior to a power off transition of a host processor coupled with the memory subsystem, and to perform a second refresh of the memory region after the power off transition of the host processor, based on the memory refresh interval corresponding to the memory region, and in response to an elapsed time since the first refresh of the memory region.

Abstract translation: 存储器保持控制器可以包括被配置为存储对应于存储器子系统中的存储器区域的存储器刷新间隔和与数据结构耦合的控制逻辑的数据结构。 控制逻辑被配置为在与存储器子系统耦合的主处理器的断电转换之前执行存储器区域的第一刷新，并且在主处理器的电源转换之后执行存储器区域的第二次刷新， 基于与存储器区域相对应的存储器刷新间隔，并且响应于自存储区域的第一次刷新以来的经过时间。