公开(公告)号：US06627477B1

公开(公告)日：2003-09-30

申请号：US09657232

申请日：2000-09-07

Applicant: Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Harold G. Linde ,  Edmund J. Sprogis

Inventor： Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Harold G. Linde ,  Edmund J. Sprogis

IPC: H01L2144

CPC classification number: H01L21/568 ,  H01L21/6835 ,  H01L24/96 ,  H01L2221/68363 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/0102 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01075

Abstract: The present invention provides a method of forming an integrated semiconductor device, and the device so formed. An active surface of at least two semiconductor devices, such as semiconductor chips, are temporarily mounted onto an alignment substrate. A support substrate is affixed to a back surface of the devices using a conformable bonding material, wherein the bonding material accommodates devices having different dimensions. The alignment substrate is then removed leaving the devices wherein the active surface of the devices are co-planar.

Abstract translation: 本发明提供一种形成集成半导体器件的方法以及如此形成的器件。 至少两个半导体器件（例如半导体芯片）的有源表面临时安装在对准衬底上。 支撑基板使用适形接合材料固定到装置的后表面，其中粘合材料容纳具有不同尺寸的装置。 然后去除对准衬底，留下其中器件的有源表面是共面的器件。

公开(公告)号：US06429045B1

公开(公告)日：2002-08-06

申请号：US09779215

申请日：2001-02-07

Applicant: Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  H. Bernhard Pogge ,  Edmund J. Sprogis ,  Steven H. Voldman

Inventor： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  H. Bernhard Pogge ,  Edmund J. Sprogis ,  Steven H. Voldman

IPC: H01L2144

CPC classification number: H01L29/0657 ,  H01L21/563 ,  H01L23/544 ,  H01L24/81 ,  H01L25/0655 ,  H01L2223/54473 ,  H01L2224/16 ,  H01L2224/73203 ,  H01L2224/81005 ,  H01L2224/81007 ,  H01L2224/81136 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10158 ,  Y10S438/928 ,  H01L2924/00012

Abstract: A technique for fabricating precision aligned macros (PAMs) with reduced risk of electrostatic discharge damage and thermal damage. An electrical and thermal contact is provided through the back of the individual chips to a supporting silicon substrate. A conductive seed layer for electroplating is formed on a support substrate. A dielectric (preferably, a thermid) layer is formed on the seed layer. Vias are formed in the thermid layer and metal contacts are formed in the vias. The front faces of two or more chips are bonded onto the top surface of an alignment substrate, and the chips are aligned to the alignment substrate. The back faces of the chips are bonded to the metal contacts and thermid layer with heat and pressure. The alignment substrate is removed. The front faces of the chips are planarized. Finally, interconnect wiring is formed over the chips and thermid layer.

Abstract translation: 一种制造精密对准宏（PAM）的技术，降低了静电放电损伤和热损伤的风险。 通过单个芯片的背面提供电接触和热接触到支撑硅衬底。 用于电镀的导电种子层形成在支撑衬底上。 在种子层上形成电介质（优选为热）层。 通孔形成在热层中，金属触点形成在通孔中。 将两个以上的芯片的正面接合在取向基板的顶面上，将芯片与取向基板对准。 芯片的背面通过热和压力结合到金属触点和热层。 取出对准基板。 芯片的正面平面化。 最后，在芯片和热层上形成互连布线。

公开(公告)号：US4801869A

公开(公告)日：1989-01-31

申请号：US42906

申请日：1987-04-27

Applicant: Edmund J. Sprogis

Inventor： Edmund J. Sprogis

IPC: H01L21/66 ,  G01R31/02 ,  G01R31/28 ,  G11C29/24 ,  G01R31/00 ,  G11C7/00

CPC classification number: G01R31/2831 ,  G01R31/024 ,  G01R31/2884 ,  G11C29/24

Abstract: A semiconductor-processing defect monitor construction for diagnosing processing-induced defects. The semiconductor-processing defect monitor utilizes an array layout and includes continuity defect monitoring structures and short-circuit defect monitoring structures. Once a defect has been indicated by a testing operation, the array layout associated with the defect monitor can be used quickly to determine the approximate location of the known defect, thereby facilitating prompt visual observation of the known defect and, thus, prompt determination of the appropriate corrective action to be applied before substantial continued manufacturing has occurred.