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201 条记录 (耗时 0.055 秒)

    Architecture and instruction set for implementing advanced encryption standard (AES)
    111.
    发明授权
    Architecture and instruction set for implementing advanced encryption standard (AES) 有权
    实现高级加密标准（AES）的体系结构和指令集

    公开(公告)号：US07949130B2

    公开(公告)日：2011-05-24

    申请号：US11648434

    申请日：2006-12-28

    申请人： Shay Gueron ,  Wajdi K. Feghali ,  Vinodh Gopal

    发明人： Shay Gueron ,  Wajdi K. Feghali ,  Vinodh Gopal

    IPC分类号： H04L9/28 ,  G06F15/00 ,  G06F12/14

    CPC分类号： H04L9/0631 ,  G06F9/30007 ,  G06F21/602 ,  H04L9/14 ,  H04L2209/24

    摘要： A flexible aes instruction for a general purpose processor is provided that performs aes encryption or decryption using n rounds, where n includes the standard aes set of rounds {10, 12, 14}. A parameter is provided to allow the type of aes round to be selected, that is, whether it is a “last round”. In addition to standard aes, the flexible aes instruction allows an AES-like cipher with 20 rounds to be specified or a “one round” pass.

    摘要翻译： 提供了一种用于通用处理器的灵活的aes指令，其使用n次循环执行aes加密或解密，其中n包括标准的一组轮{10,12,14}。 提供了一个参数，以允许选择一轮的类型，即是否是“最后一轮”。 除了标准aes之外，灵活的aes指令允许指定具有20发的AES类密码或“一轮”通过。

    INSTRUCTION AND LOGIC TO PROVIDE A SECURE CIPHER HASH ROUND FUNCTIONALITY
    113.
    发明申请
    INSTRUCTION AND LOGIC TO PROVIDE A SECURE CIPHER HASH ROUND FUNCTIONALITY 审中-公开
    指导和逻辑提供安全的水龙头功能

    公开(公告)号：US20150043729A1

    公开(公告)日：2015-02-12

    申请号：US13962933

    申请日：2013-08-08

    申请人： Vinodh Gopal ,  Wajdi K. Feghali

    发明人： Vinodh Gopal ,  Wajdi K. Feghali

    IPC分类号： H04L9/06

    CPC分类号： H04L9/0643 ,  G06F9/30007 ,  G06F9/30036 ,  H04L9/0625

    摘要： Instructions and logic provide secure cipher hashing algorithm round functionality. Some embodiments include a processor comprising: a decode stage to decode an instruction for a secure cipher hashing algorithm, the first instruction specifying a source data, and one or more key operands. Processor execution units, are responsive to the decoded instruction, to perform one or more secure cipher hashing algorithm round iterations upon the source data, using the one or more key operands, and store a result of the instruction in a destination register. One embodiment of the instruction specifies a secure cipher hashing algorithm round iteration using a Feistel cipher algorithm such as DES or TDES. In one embodiment a result of the instruction may be used in generating a resource assignment from a request for load balancing requests across the set of processing resources.

    摘要翻译： 指令和逻辑提供安全密码散列算法的圆功能。 一些实施例包括处理器，包括：解码级，用于解码用于安全密码散列算法的指令，指定源数据的第一指令以及一个或多个键操作数。 处理器执行单元响应于解码的指令，使用一个或多个键操作数对源数据执行一次或多次安全密码散列算法循环迭代，并将该指令的结果存储在目的地寄存器中。 该指令的一个实施例使用诸如DES或TDES之类的Feistel密码算法来指定安全密码散列算法的圆迭代。 在一个实施例中，指令的结果可以用于从整个处理资源集合的负载平衡请求请求生成资源分配。

    ARCHITECTURE AND INSTRUCTION SET FOR IMPLEMENTING ADVANCED ENCRYPTION STANDARD (AES)
    116.
    发明申请
    ARCHITECTURE AND INSTRUCTION SET FOR IMPLEMENTING ADVANCED ENCRYPTION STANDARD (AES) 有权
    实施高级加密标准（AES）的架构和指导

    公开(公告)号：US20120002804A1

    公开(公告)日：2012-01-05

    申请号：US13088088

    申请日：2011-04-15

    申请人： Shay Gueron ,  Wajdi K. Feghali ,  Vinodh Gopal

    发明人： Shay Gueron ,  Wajdi K. Feghali ,  Vinodh Gopal

    IPC分类号： H04L9/28

    CPC分类号： H04L9/0631 ,  G06F9/30007 ,  G06F21/602 ,  H04L9/14 ,  H04L2209/24

    摘要： A flexible aes instruction for a general purpose processor is provided that performs aes encryption or decryption using n rounds, where n includes the standard aes set of rounds {10, 12, 14}. A parameter is provided to allow the type of aes round to be selected, that is, whether it is a “last round”. In addition to standard aes, the flexible aes instruction allows an AES-like cipher with 20 rounds to be specified or a “one round” pass.

    摘要翻译： 提供了一种用于通用处理器的灵活的aes指令，其使用n次循环执行aes加密或解密，其中n包括标准的一组轮{10,12,14}。 提供了一个参数，以允许选择一轮的类型，即是否是“最后一轮”。 除了标准aes之外，灵活的aes指令允许指定具有20发的AES类密码或“一轮”通过。

    Factoring Based Modular Exponentiation
    117.
    发明申请
    Factoring Based Modular Exponentiation 有权
    基于分数的模块化指数

    公开(公告)号：US20080144810A1

    公开(公告)日：2008-06-19

    申请号：US11610886

    申请日：2006-12-14

    申请人： Vinodh Gopal ,  Erdinc Ozturk ,  Matt Bace ,  Wajdi Feghali ,  Robert P. Ottavi

    发明人： Vinodh Gopal ,  Erdinc Ozturk ,  Matt Bace ,  Wajdi Feghali ,  Robert P. Ottavi

    IPC分类号： H04L9/30

    CPC分类号： G06F7/723

    摘要： The present disclosure provides a system and method for performing modular exponentiation. The method may include dividing a first polynomial into a plurality of segments and generating a first product by multiplying the plurality of segments of the first polynomial with a second polynomial. The method may also include generating a second product by shifting the contents of an accumulator with a factorization base. The method may further include adding the first product and the second product to yield a first intermediate result and reducing the first intermediate result to yield a second intermediate result. The method may also include generating a public key based on, at least in part, the second intermediate result. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.

    摘要翻译： 本公开提供了一种用于执行模幂运算的系统和方法。 该方法可以包括将第一多项式划分成多个段，并通过将第一多项式的多个段乘以第二多项式来生成第一乘积。 该方法还可以包括通过用因式分解基座移位累加器的内容来产生第二乘积。 该方法还可以包括添加第一产物和第二产物以产生第一中间结果并减少第一中间结果以产生第二中间结果。 该方法还可以包括至少部分地基于第二中间结果生成公钥。 当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

    METHODS, SYSTEMS AND APPARATUS TO REDUCE PROCESSOR DEMANDS DURING ENCRYPTION
    118.
    发明申请
    METHODS, SYSTEMS AND APPARATUS TO REDUCE PROCESSOR DEMANDS DURING ENCRYPTION 有权
    在加密过程中减少处理器数量的方法，系统和设备

    公开(公告)号：US20140177823A1

    公开(公告)日：2014-06-26

    申请号：US13727141

    申请日：2012-12-26

    申请人： Vinodh Gopal ,  Erdinc Ozturk ,  James D. Guilford

    发明人： Vinodh Gopal ,  Erdinc Ozturk ,  James D. Guilford

    IPC分类号： H04L9/28

    CPC分类号： H04L9/0637 ,  G06F9/00 ,  G06F9/30032 ,  G06F21/00 ,  H04L2209/12

    摘要： Methods and apparatus are disclosed to reduce processor demands during encryption. A disclosed example method includes detecting a request for the processor to execute an encryption cipher determining whether the encryption cipher is associated with a byte reflection operation, preventing the byte reflection operation when a buffer associated with the encryption cipher will not cause a carryover condition, and incrementing the buffer via a shift operation before executing the encryption cipher.

    摘要翻译： 公开了减少加密期间处理器需求的方法和装置。 所公开的示例方法包括：检测处理器执行确定加密密码是否与字节反射操作相关联的加密密码的请求，当与加密密码相关联的缓冲器不会导致携带条件时，防止字节反射操作;以及 在执行加密密码之前通过移位操作递增缓冲区。

    Factoring based modular exponentiation
    119.
    发明授权
    Factoring based modular exponentiation 有权
    基于分数的模幂运算

    公开(公告)号：US07961877B2

    公开(公告)日：2011-06-14

    申请号：US11610886

    申请日：2006-12-14

    申请人： Vinodh Gopal ,  Erdinc Ozturk ,  Matt Bace ,  Wajdi Feghali ,  Robert P. Ottavi

    发明人： Vinodh Gopal ,  Erdinc Ozturk ,  Matt Bace ,  Wajdi Feghali ,  Robert P. Ottavi

    IPC分类号： H04L9/30 ,  H04L9/28 ,  H04L9/00 ,  G06G7/16

    CPC分类号： G06F7/723

    摘要： The present disclosure provides a system and method for performing modular exponentiation. The method may include dividing a first polynomial into a plurality of segments and generating a first product by multiplying the plurality of segments of the first polynomial with a second polynomial. The method may also include generating a second product by shifting the contents of an accumulator with a factorization base. The method may further include adding the first product and the second product to yield a first intermediate result and reducing the first intermediate result to yield a second intermediate result. The method may also include generating a public key based on, at least in part, the second intermediate result. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.

    摘要翻译： 本公开提供了一种用于执行模幂运算的系统和方法。 该方法可以包括将第一多项式划分成多个段，并通过将第一多项式的多个段乘以第二多项式来生成第一乘积。 该方法还可以包括通过用因式分解基座移位累加器的内容来产生第二乘积。 该方法还可以包括添加第一产物和第二产物以产生第一中间结果并减少第一中间结果以产生第二中间结果。 该方法还可以包括至少部分地基于第二中间结果生成公钥。 当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

    RESIDUE GENERATION
    120.
    发明申请
    RESIDUE GENERATION 失效
    残留生成

    公开(公告)号：US20100153829A1

    公开(公告)日：2010-06-17

    申请号：US12336029

    申请日：2008-12-16

    申请人： Vinodh Gopal ,  Erdinc Ozturk ,  Gilbert Wolrich ,  Wajdi Feghali

    发明人： Vinodh Gopal ,  Erdinc Ozturk ,  Gilbert Wolrich ,  Wajdi Feghali

    IPC分类号： H03M13/09 ,  G06F7/72 ,  G06F11/10

    CPC分类号： G06F7/724 ,  H03M13/091

    摘要： In one embodiment, circuitry is provided to generate a residue based at least in part upon operations and a data stream generated based at least in part upon a packet. The operations may include at least one iteration of at least one reduction operation including (a) multiplying a first value with at least one portion of the data stream, and (b) producing a reduction by adding at least one other portion of the data stream to a result of the multiplying. The operations may include at least one other reduction operation including (c) producing another result by multiplying with a second value at least one portion of another stream based at least in part upon the reduction, (d) producing a third value by adding at least one other portion of the another stream to the another result, and (e) producing the residue by performing a Barrett reduction based at least in part upon the third value.

    摘要翻译： 在一个实施例中，提供电路以至少部分地基于至少部分地基于分组产生的操作和数据流来生成残差。 操作可以包括至少一个缩减操作的迭代，包括（a）将第一值与数据流的至少一部分相乘，以及（b）通过添加数据流的至少一个其他部分来产生减少 是乘法的结果。 所述操作可以包括至少一个其它减少操作，其包括（c）至少部分地基于所述减少，通过与另一个流的至少一部分乘以第二值来产生另一结果，（d）通过至少加入来产生第三值 另一个流的另一部分到另一个结果，以及（e）至少部分地基于第三个值执行巴雷特还原来产生残留物。