公开(公告)号：US20210296175A1

公开(公告)日：2021-09-23

申请号：US17338296

申请日：2021-06-03

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Feras Eid ,  Telesphor Kamgaing ,  Georgios Dogiamis ,  Johanna M. Swan

IPC: H01L21/768 ,  H01L23/00

Abstract: Disclosed herein are methods to fabricate inorganic dies with organic interconnect layers and related structures and devices. In some embodiments, an integrated circuit (IC) structure may be formed to include an inorganic die and one or more organic interconnect layers on the inorganic die, wherein the organic interconnect layers include an organic dielectric. An example method includes forming organic interconnect layers over an inorganic interconnect substrate and forming passive components in the organic interconnect layer. The organic interconnect layers comprise a plurality of conductive metal layers through an organic dielectric material. The plurality of conductive metal layers comprises electrical pathways. the passive components are electrically coupled to the electrical pathways.

公开(公告)号：US20210233856A1

公开(公告)日：2021-07-29

申请号：US17229991

申请日：2021-04-14

Applicant: Intel Corporation

Inventor： Georgios Dogiamis ,  Aleksandar Aleksov ,  Feras Eid ,  Telesphor Kamgaing ,  Johanna M. Swan

IPC: H01L23/538 ,  B81B7/00 ,  H01L23/28 ,  H01L23/552 ,  H01L21/56

Abstract: Embodiments may relate to a microelectronic package that includes an overmold material, a redistribution layer (RDL) in the overmold material, and a die in the overmold material electrically coupled with the RDL on an active side of the die. The RDL is configured to provide electrical interconnection within the overmold material and includes at least one mold interconnect. The microelectronic package may also include a through-mold via (TMV) disposed in the overmold material and electrically coupled to the RDL by the mold interconnect. In some embodiments, the microelectronics package further includes a surface mount device (SMD) in the overmold material. The microelectronics package may also include a substrate having a face on which the overmold is disposed.

公开(公告)号：US11062947B1

公开(公告)日：2021-07-13

申请号：US16721235

申请日：2019-12-19

Applicant: INTEL CORPORATION

Inventor： Aleksandar Aleksov ,  Feras Eid ,  Telesphor Kamgaing ,  Georgios Dogiamis ,  Johanna M. Swan

IPC: H01L21/768 ,  H01L23/00

Abstract: Disclosed herein are inorganic dies with organic interconnect layers and related structures, devices, and methods. In some embodiments, an integrated circuit (IC) structure may include an inorganic die and one or more organic interconnect layers on the inorganic die, wherein the organic interconnect layers include an organic dielectric.

公开(公告)号：US11056765B2

公开(公告)日：2021-07-06

申请号：US16345173

申请日：2016-12-20

Applicant: Intel Corporation

Inventor： Telesphor Kamgaing ,  Georgios C. Dogiamis ,  Sasha N. Oster

IPC: H01Q1/22 ,  H01L23/31 ,  H01L23/538 ,  H01L23/66 ,  H01L25/065 ,  H01Q1/38 ,  H01L23/13 ,  H01Q9/04 ,  H01Q13/10 ,  H01L23/00 ,  H01L23/498 ,  H01Q21/06

Abstract: Embodiments of the invention include a microelectronic device that includes a first substrate having radio frequency (RF) circuits and a second substrate coupled to the first substrate. The second substrate includes a first section and a second section with the second substrate being foldable in order to obtain a desired orientation of an antenna unit of the second section for transmitting and receiving communications at a frequency of approximately 4 GHz or higher.

公开(公告)号：US11024933B2

公开(公告)日：2021-06-01

申请号：US16325351

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Brandon M. Rawlings ,  Shawna M. Liff ,  Sasha N. Oster ,  Georgios C. Dogiamis ,  Telesphor Kamgaing ,  Adel A. Elsherbini ,  Aleksandar Aleksov ,  Johanna M. Swan ,  Richard J. Dischler

IPC: H01P3/16 ,  H01P3/12 ,  H01P3/123 ,  H01P3/14 ,  H01P11/00

Abstract: A method of making a waveguide, comprises: extruding a first dielectric material as a waveguide core of the waveguide, wherein the waveguide core is elongate; and coextruding an outer layer with the waveguide core, wherein the outer layer is arranged around the waveguide core.

公开(公告)号：US20210160999A1

公开(公告)日：2021-05-27

申请号：US16697699

申请日：2019-11-27

Applicant: Intel Corporation

Inventor： Georgios Dogiamis ,  Aleksandar Aleksov ,  Feras Eid ,  Telesphor Kamgaing ,  Johanna M. Swan

IPC: H05K1/02 ,  H05K1/16 ,  H05K3/12 ,  H05K3/40

Abstract: Embodiments may relate to a microelectronic package or a die thereof which includes a die, logic, or subsystem coupled with a face of the substrate. An inductor may be positioned in the substrate. Electromagnetic interference (EMI) shield elements may be positioned within the substrate and surrounding the inductor. Other embodiments may be described or claimed.

公开(公告)号：US11011470B1

公开(公告)日：2021-05-18

申请号：US16667698

申请日：2019-10-29

Applicant: Intel Corporation

Inventor： Georgios Dogiamis ,  Aleksandar Aleksov ,  Feras Eid ,  Telesphor Kamgaing ,  Johanna M. Swan

IPC: H01L23/538 ,  B81B7/00 ,  H01L23/28 ,  H01L23/552 ,  H01L21/56

Abstract: Embodiments may relate to a microelectronic package that includes a substrate with an overmold material. The microelectronic package may include a die in the overmold material, and an inactive side of the die may be coupled with a face of the substrate. A through-mold via (TMV) may be present in the overmold material. The TMV may be communicatively coupled with the substrate, and an active side of the die may be communicatively coupled with the TMV by a trace in the overmold material. Other embodiments may be described or claimed.

公开(公告)号：US20210066265A1

公开(公告)日：2021-03-04

申请号：US16553544

申请日：2019-08-28

Applicant: Intel Corporation

Inventor： Feras Eid ,  Aleksandar Aleksov ,  Telesphor Kamgaing ,  Georgios Dogiamis ,  Johanna M. Swan ,  Sivakumar Nagarajan ,  Nitin A. Deshpande ,  Omkar G. Karhade ,  William James Lambert

IPC: H01L25/16 ,  H01L23/13 ,  H01L23/498 ,  H01L23/00 ,  H03F3/213 ,  H01G2/06 ,  H01G2/10

Abstract: Disclosed herein are tunable capacitor arrangements in integrated circuit (IC) package substrates, as well as related methods and devices. For example, in some embodiments, an IC package substrate may include a first embedded capacitor, a second embedded capacitor, and a fuse electrically coupled between the first embedded capacitor and the second embedded capacitor such that when the fuse is in a closed state, the first embedded capacitor and the second embedded capacitor are connected in parallel, and when the fuse is in an open state, the first embedded capacitor and the second embedded capacitor are not connected in parallel.

公开(公告)号：US20210066184A1

公开(公告)日：2021-03-04

申请号：US16554288

申请日：2019-08-28

Applicant: INTEL CORPORATION

Inventor： Aleksandar Aleksov ,  Feras Eid ,  Georgios Dogiamis ,  Telesphor Kamgaing ,  Johanna M. Swan

IPC: H01L23/522 ,  H01L23/495 ,  H01L23/00 ,  H01L49/02

Abstract: Disclosed herein are capacitor-wirebond pad structures for integrated circuit (IC) packages, as well as related methods and devices. For example, in some embodiments, an IC package may include a die and an IC package support. The IC package support may include a capacitor, and the capacitor may include a first capacitor plate, a second capacitor plate, and a capacitor dielectric between the first capacitor plate and the second capacitor plate. The die may be wirebonded to the first capacitor plate.

公开(公告)号：US20210043544A1

公开(公告)日：2021-02-11

申请号：US16533152

申请日：2019-08-06

Applicant: Intel Corporation

Inventor： Feras Eid ,  Telesphor Kamgaing ,  Georgios Dogiamis ,  Aleksandar Aleksov ,  Johanna M. Swan

IPC: H01L23/427 ,  H01L23/38 ,  H01L23/373 ,  H01L23/31 ,  H01L23/66 ,  H01L23/48 ,  H03H9/46

Abstract: Disclosed herein are structures and assemblies that may be used for thermal management in integrated circuit (IC) packages.