公开(公告)号：US20180308917A1

公开(公告)日：2018-10-25

申请号：US15942452

申请日：2018-03-31

Applicant: Innolux Corporation

Inventor： Pai-Chiao Cheng ,  Hsia-Ching Chu ,  Kuan-Feng Lee ,  Chandra Lius ,  Pei-Chieh Chen

IPC: H01L27/32 ,  G09G3/3258 ,  G09G3/34

CPC classification number: H01L27/3276 ,  G09G3/3258 ,  G09G3/34 ,  G09G2310/0264 ,  H01L27/1214 ,  H01L27/1244

Abstract: A display device including a substrate, first and second reference voltage lines, a first insulation layer is provided. The first and second reference voltage lines are disposed in a peripheral area of the substrate. The first insulation layer having a groove is disposed on the first reference voltage line. The groove extends along a first direction and exposes a contact portion of the first reference voltage line. The first insulation layer covers a first covered portion of the first reference voltage line. The second reference voltage line contacts the contact portion at the groove and has a contact surface. In a second direction, a first width W1 of the contact surface, a second width W2 of the first reference voltage line and a third width W3 of the first covered portion are complied with 1≤W1≤(W2-W3), wherein W3 is greater than 0 and smaller than W2.

公开(公告)号：US10074669B2

公开(公告)日：2018-09-11

申请号：US15480423

申请日：2017-04-06

Applicant: InnoLux Corporation

Inventor： Chandra Lius

IPC: H01L27/12 ,  H01L29/24 ,  H01L29/786 ,  H01L29/423

CPC classification number: H01L27/1225 ,  G02F1/133345 ,  G02F1/13338 ,  G02F1/134309 ,  G02F1/1368 ,  G02F2001/133388 ,  G02F2001/13685 ,  G06F3/0412 ,  H01L27/1222 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1251 ,  H01L27/1255 ,  H01L27/323 ,  H01L27/3262 ,  H01L27/3276 ,  H01L29/24 ,  H01L29/42356 ,  H01L29/4908 ,  H01L29/78648 ,  H01L29/78672 ,  H01L29/78675 ,  H01L29/7869 ,  H01L29/78696

Abstract: A display device is disclosed, which includes: a substrate having a display region and a peripheral region adjacent to the display region; a first transistor disposed on the display region and comprising a first channel layer, wherein the first channel layer includes an oxide semiconductor layer; and a second transistor disposed on the peripheral region and comprising a second channel layer, wherein the second channel layer includes a silicon semiconductor layer. Herein, a first ratio, which is a ratio of a first channel width of the first channel layer to the first channel length thereof, is greater than or equal to 0.4 and less than or equal to 4.5; and a second ratio, which is a ratio of a second channel width of the second channel layer to a second channel length thereof, is greater than or equal to 0.05 and less than or equal to 0.8.