公开(公告)号：US20210173770A1

公开(公告)日：2021-06-10

申请号：US17181718

申请日：2021-02-22

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Gary L. Howe

IPC: G06F12/02 ,  G06F12/0855 ,  G06F13/16

Abstract: The present disclosure includes apparatuses and methods related to shifting data. An example apparatus comprises a cache coupled to an array of memory cells and a controller. The controller is configured to perform a first operation beginning at a first address to transfer data from the array of memory cells to the cache, and perform a second operation concurrently with the first operation, the second operation beginning at a second address.

公开(公告)号：US10929023B2

公开(公告)日：2021-02-23

申请号：US16541764

申请日：2019-08-15

Applicant: Micron Technology, Inc.

Inventor： Thanh K. Mai ,  Gary L. Howe ,  Daniel B. Penney

IPC: G06F3/06 ,  G11C8/00 ,  G06F13/16

Abstract: The present disclosure includes apparatuses and methods to transfer data between banks of memory cells. An example includes a plurality of banks of memory cells and a controller coupled to the plurality of subarrays configured to cause transfer of data between the plurality of banks of memory cells via internal data path operations.

公开(公告)号：US10892006B1

公开(公告)日：2021-01-12

申请号：US16786661

申请日：2020-02-10

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Gary L. Howe

IPC: G11C11/40 ,  G11C11/4096 ,  G11C11/4076

Abstract: A memory device include write leveling circuitry that is configured to receive a write command from the command interface. The write leveling circuitry also receives a data strobe (DQS) signal from a host device (e.g., processor) and receives a clock signal from the host device. The write leveling circuitry also compares phases of the DQS signal and the clock signal using a phase detector. The write leveling circuitry also generates an internal write signal (IWS) based upon the write command, and outputs a captured result of a write leveling operation based at least in part on the compared phases and the IWS.

公开(公告)号：US10832760B2

公开(公告)日：2020-11-10

申请号：US16690598

申请日：2019-11-21

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  David R. Brown ,  Gary L. Howe

IPC: G11C29/02 ,  G11C11/4093 ,  G11C7/10 ,  G11C11/4076

Abstract: A memory device includes a data write circuitry. The data write circuitry is configured to capture a first write command received via an external input/output (I/O) interface. The data write circuitry is further configured to generate a first internal write start (InternalWrStart) in a data strobe (DQS) domain after capture of the first write command. The data write circuitry is additionally configured to write a first one or more data bits into at least one memory bank based on the first InternalWrStart, wherein the first InternalWrStart is generated internally in the memory device.

公开(公告)号：US10672441B2

公开(公告)日：2020-06-02

申请号：US16051202

申请日：2018-07-31

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Liang Chen ,  David R. Brown

IPC: G11C7/00 ,  G11C7/22 ,  G11C7/10 ,  G11C11/4076 ,  G11C11/4093 ,  G11C8/18 ,  G11C8/10 ,  G11C11/4096 ,  H04L25/03 ,  G06F13/18 ,  G11C11/4074

Abstract: Method and devices include a shifter that is configured to receive a write command for a memory device and is configured to produce multiple shifted write commands from the write command. Multiple flip-flops that are configured to receive a subset of the multiple shifted write commands from the shifter. The multiple flip-flops also are configured to output an indicator of whether subsequent write commands of the subset of write commands is asserted when the write command has completed shifting through the shifter as a write start signal.

公开(公告)号：US10664173B2

公开(公告)日：2020-05-26

申请号：US15883956

申请日：2018-01-30

Applicant: Micron Technology, Inc.

Inventor： Gary Howe ,  Liang Chen ,  Daniel B. Penney

IPC: G11B5/00 ,  G06F3/06

Abstract: Techniques provided herein compensate for an internal and external timing skew between a data strobe (DQS) and a clock (CLK), by: executing at least one write leveling initialization procedure (WLInit) that uses a mode-register-write (MRW) command to synchronize a timing between a data strobe (DQS) with a clock (CLK) based upon capture of an internal write command. Internal and external timing skew is identified based upon the WLInit. The internal timing skew is skew caused internal to a memory device and the external timing skew is skew caused external to the memory device. A timing between the DQS and the CLK is adjusted based upon the internal and external timing skew.

公开(公告)号：US20200135263A1

公开(公告)日：2020-04-30

申请号：US16176932

申请日：2018-10-31

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jason M. Brown ,  Daniel B. Penney

IPC: G11C11/406 ,  G11C16/34 ,  G11C11/4076 ,  G11C7/10 ,  G06F11/30

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for scheduling targeted refreshes in a memory device. Memory cells in a memory device may be volatile and may need to be periodically refreshed as part of an auto-refresh operation. In addition, certain rows may experience faster degradation, and may need to undergo targeted refresh operations, where a specific targeted refresh address is provided and refreshed. The rate at which targeted refresh operations need to occur may be based on the rate at which memory cells are accessed. The memory device may monitor accesses to a bank of the memory, and may use a count of the accesses to determine if an auto-refresh address or a targeted refresh address will be refreshed.

公开(公告)号：US20200090732A1

公开(公告)日：2020-03-19

申请号：US16690598

申请日：2019-11-21

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  David R. Brown ,  Gary L. Howe

IPC: G11C11/4093 ,  G11C7/10

Abstract: A memory device includes a data write circuitry. The data write circuitry is configured to capture a first write command received via an external input/output (I/O) interface. The data write circuitry is further configured to generate a first internal write start (InternalWrStart) in a data strobe (DQS) domain after capture of the first write command. The data write circuitry is additionally configured to write a first one or more data bits into at least one memory bank based on the first InternalWrStart, wherein the first InternalWrStart is generated internally in the memory device.

公开(公告)号：US20200082856A1

公开(公告)日：2020-03-12

申请号：US16683018

申请日：2019-11-13

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Liang Chen ,  David R. Brown

IPC: G11C7/22 ,  G11C7/10 ,  G11C11/4074 ,  G06F13/18 ,  H04L25/03 ,  G11C11/4096 ,  G11C8/10 ,  G11C8/18 ,  G11C11/4093 ,  G11C11/4076

Abstract: Methods and devices include an input buffer configured to receive data. Decision feedback equalizer (DFE) circuitry includes a DFE configured to interpret levels of the data from the input buffer and a DFE buffer that stores previous values to control the DFE based on the previous values. Moreover, the DFE circuitry also includes reset circuitry configured to reset the DFE buffer to an initial state. Furthermore, the DFE circuitry includes suppression circuitry configured to suppress resets using the reset circuitry for an interval between write operations to the memory device.

公开(公告)号：US10535387B2

公开(公告)日：2020-01-14

申请号：US15891353

申请日：2018-02-07

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Liang Chen

IPC: G11C7/00 ,  G11C8/18 ,  G11C7/10 ,  G06F5/06 ,  G06F13/42 ,  G11C29/50 ,  G06F13/16

Abstract: Memory devices and methods include receiving data at an input buffer and outputting serial data. The serial shift data is passed toward a serial shift register that shifts its stored data into a data write bus in a parallel format. Serial shift register loading circuitry controls loading of a serial shift register. The serial shift register loading circuitry is configured to receive a data strobe signal and provide the data strobe to the serial shift register to cause the serial shift register to shift in the serial data during a write operation. The serial register loading circuitry includes gating circuitry that is configured to cutoff provision of the data strobe from the serial register loading circuitry based at least in part on a load signal that indicates that the data write bus has been loaded with the serial data in a parallel format.