公开(公告)号：US11302395B2

公开(公告)日：2022-04-12

申请号：US16451143

申请日：2019-06-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Haitao Liu

IPC: G11C16/04 ,  G11C5/06 ,  H01L27/11524 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11529

Abstract: Apparatus having a transistor connected between a voltage node and a load node, where the transistor includes a dielectric overlying a semiconductor having a first conductivity type, a conductor overlying the dielectric, first and second extension region bases formed in the semiconductor and having a second conductivity type, first and second extension region risers formed overlying respective first and second extension region bases and having the second conductivity type, and first and second source/drain regions formed in respective first and second extension region risers and having the second conductivity type at greater conductivity levels than their respective extension region risers, as well as method of forming similar transistors.

公开(公告)号：US20210408244A1

公开(公告)日：2021-12-30

申请号：US17468936

申请日：2021-09-08

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Haitao Liu ,  Chandra Mouli

IPC: H01L21/28 ,  G11C16/04 ,  H01L21/763

Abstract: Field-effect transistors, and methods of forming such field-effect transistors, including a gate dielectric overlying a semiconductor material, and a control gate overlying the gate dielectric, wherein the control gate includes an instance of a first polycrystalline silicon-containing material consisting essentially of polycrystalline silicon, and an instance of a second polycrystalline silicon-containing material selected from a group consisting of polycrystalline silicon-germanium and polycrystalline silicon-germanium-carbon.

公开(公告)号：US20210375893A1

公开(公告)日：2021-12-02

申请号：US17445134

申请日：2021-08-16

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Akira Goda ,  Sanh D. Tang ,  Gurtej S. Sandhu ,  Litao Yang ,  Haitao Liu

IPC: H01L27/11524 ,  H01L27/1157 ,  H01L29/24 ,  H01L29/786 ,  H01L23/522 ,  H01L27/11556 ,  H01L27/11582 ,  H01L23/528

Abstract: A transistor comprises a 2D material structure and a gate structure. The 2D material structure conformally extends on and between surfaces of dielectric fin structures extending in parallel in a first horizontal direction, and comprises a source region, a drain region, and a channel region positioned between the source region and the drain region in the first horizontal direction. The gate structure overlies the channel region of the 2D material structure and extends in a second horizontal direction orthogonal to the first horizontal direction. The gate structure is within horizontal boundaries of the channel region of the 2D material structure in the first horizontal direction. Microelectronic devices, memory devices, and electronic systems are also described.

公开(公告)号：US11177265B2

公开(公告)日：2021-11-16

申请号：US16862122

申请日：2020-04-29

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Si-Woo Lee ,  Haitao Liu ,  Deepak Chandra Pandey

IPC: H01L27/108 ,  H01L29/10 ,  H01L29/49 ,  H01L29/167

Abstract: Some embodiments include an integrated assembly having an active-region-pillar extending upwardly from a base. The active-region-pillar includes a digit-line-contact-region between a first storage-element-contact-region and a second storage-element-contact-region. A threshold-voltage-inducing-structure is adjacent a lower portion of the active-region-pillar. A first channel region includes a first portion of the active-region-pillar between the digit-line-contact-region and the first storage-element-contact-region. A second channel region includes a second portion of the active-region-pillar between the digit-line-contact-region and the second storage-element-contact-region. A first wordline is adjacent the first portion of the active-region-pillar. A second wordline is adjacent the second portion of the active-region-pillar. A digit-line is coupled with the digit-line-contact-region. First and second storage-elements are coupled with the first and second storage-element-contact-regions. A voltage source is coupled with the threshold-voltage-inducing-structure to electrostatically induce a desired threshold voltage along the first and second channel regions.

公开(公告)号：US11171206B2

公开(公告)日：2021-11-09

申请号：US16509093

申请日：2019-07-11

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Haitao Liu ,  Si-Woo Lee ,  Fatma Arzum Simsek-Ege ,  Deepak Chandra Pandey ,  Chandra V. Mouli ,  John A. Smythe, III

IPC: H01L29/06 ,  H01L27/108 ,  H01L21/762

Abstract: An example apparatus includes a first source/drain region and a second source/drain region formed in a substrate to form an active area of the apparatus. The first source/drain region and the second source/drain region are separated by a channel. The apparatus includes a gate opposing the channel. A sense line is coupled to the first source/drain region and a storage node is coupled to the second source/drain region. An isolation trench is adjacent to the active area. The trench includes a dielectric material with a conductive bias opposing the conductive bias of the channel in the active area.

公开(公告)号：US11139396B2

公开(公告)日：2021-10-05

申请号：US16596090

申请日：2019-10-08

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Durai Vishak Nirmal Ramaswamy ,  Haitao Liu

IPC: H01L29/78 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

Abstract: A device comprises a first conductive line and a vertical transistor over the first conductive line. The vertical transistor comprises a gate electrode, a gate dielectric material overlying sides of the gate electrode, and a channel region on sides of the gate dielectric material, the gate dielectric material located between the channel region and the gate electrode. The device further comprises a second conductive line overlying a conductive contact of the at least one vertical transistor. Related devices and methods of forming the devices are also disclosed.

公开(公告)号：US11127747B2

公开(公告)日：2021-09-21

申请号：US16549519

申请日：2019-08-23

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Akira Goda ,  Sanh D. Tang ,  Gurtej S. Sandhu ,  Litao Yang ,  Haitao Liu

IPC: H01L27/11524 ,  H01L27/1157 ,  H01L29/24 ,  H01L29/786 ,  H01L23/522 ,  H01L27/11556 ,  H01L27/11582 ,  H01L23/528

Abstract: A transistor comprises a 2D material structure and a gate structure. The 2D material structure conformally extends on and between surfaces of dielectric fin structures extending in parallel in a first horizontal direction, and comprises a source region, a drain region, and a channel region positioned between the source region and the drain region in the first horizontal direction. The gate structure overlies the channel region of the 2D material structure and extends in a second horizontal direction orthogonal to the first horizontal direction. The gate structure is within horizontal boundaries of the channel region of the 2D material structure in the first horizontal direction. Microelectronic devices, memory devices, and electronic systems are also described.

公开(公告)号：US20210257387A1

公开(公告)日：2021-08-19

申请号：US17308766

申请日：2021-05-05

Applicant: Micron Technology, Inc.

Inventor： Guangyu Huang ,  Haitao Liu ,  Chandra Mouli ,  Justin B. Dorhout ,  Sanh D. Tang ,  Akira Goda

IPC: H01L27/11582 ,  H01L23/522 ,  H01L27/1157 ,  H01L49/02

Abstract: Some embodiments include an integrated structure having vertically-stacked conductive levels. Upper conductive levels are memory cell levels, and a lower conductive level is a select device level. Conductively-doped semiconductor material is under the select device level. Channel material extends along the memory cell levels and the select device level, and extends into the conductively-doped semiconductor material. A region of the channel material that extends into the conductively-doped semiconductor material is a lower region of the channel material and has a vertical sidewall. Tunneling material, charge-storage material and charge-blocking material extend along the channel material and are between the channel material and the conductive levels. The tunneling material, charge-storage material and charge-blocking material are not along at least a portion of the vertical sidewall of the lower region of the channel material, and the conductively-doped semiconductor material is directly against such portion. Some embodiments include methods of forming integrated structures.

公开(公告)号：US11069687B2

公开(公告)日：2021-07-20

申请号：US16809924

申请日：2020-03-05

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Srinivas Pulugurtha ,  Richard J. Hill ,  Yunfei Gao ,  Nicholas R. Tapias ,  Litao Yang ,  Haitao Liu

IPC: H01L27/108

Abstract: Some embodiments include an integrated assembly having digit lines which extend along a first direction, and which are spaced from one another by intervening regions. Each of the intervening regions has a first width along a cross-section. Pillars extend upwardly from the digit lines; and the pillars include transistor channel regions extending vertically between upper and lower source/drain regions. Storage elements are coupled with the upper source/drain regions. Wordlines extend along a second direction which crosses the first direction. The wordlines include gate regions adjacent the channel regions. Shield lines are within the intervening regions and extend along the first direction. The shield lines may be coupled with at least one reference voltage node. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11018255B2

公开(公告)日：2021-05-25

申请号：US16110217

申请日：2018-08-23

Applicant: Micron Technology, Inc.

Inventor： Haitao Liu ,  Guangyu Huang ,  Chandra V. Mouli ,  Akira Goda ,  Deepak Chandra Pandey ,  Kamal M. Karda

IPC: H01L29/78 ,  H01L29/24 ,  H01L29/423 ,  H01L29/267 ,  H01L27/11556 ,  H01L29/66 ,  H01L21/02 ,  H01L21/44 ,  H01L27/11582 ,  H01L29/08 ,  H01L21/425 ,  H01L29/10 ,  H01L29/786 ,  H01L27/1157 ,  H01L29/36 ,  H01L29/49 ,  H01L29/417

Abstract: A device includes a string driver comprising a channel region between a drain region and a source region. At least one of the channel region, the drain region, and the source region comprises a high band gap material. A gate region is adjacent and spaced from the high band gap material. The string driver is configured for high-voltage operation in association with an array of charge storage devices (e.g., 2D NAND or 3D NAND). Additional devices and systems (e.g., non-volatile memory systems) including the string drivers are disclosed, as are methods of forming the string drivers.