公开(公告)号：US20220107735A1

公开(公告)日：2022-04-07

申请号：US17552060

申请日：2021-12-15

Applicant: Micron Technology, Inc.

Inventor： Paolo Amato ,  Daniele Balluchi ,  Danilo Caraccio ,  Emanuele Confalonieri ,  Marco Dallabora

IPC: G06F3/06 ,  G06F12/1009 ,  G11C16/34 ,  G06F11/10

Abstract: The present disclosure includes apparatuses and methods related to memory operations on data. An example method can include executing an operation by writing a first managed unit to a second managed unit, and placing the first managed unit in a free state, wherein the first managed unit is located at a particular distance from the second managed unit.

公开(公告)号：US11256565B2

公开(公告)日：2022-02-22

申请号：US16931787

申请日：2020-07-17

Applicant: Micron Technology, Inc.

Inventor： Graziano Mirichigni ,  Marco Sforzin ,  Paolo Amato ,  Danilo Caraccio

IPC: H03M13/00 ,  G06F11/10 ,  G06F9/46 ,  G06F13/16

Abstract: Apparatuses and methods related to providing transaction metadata. Providing transaction metadata includes providing an address of data stored in the memory device using an address bus coupled to the memory device and the controller. Providing transaction metadata also includes transferring the data, associated with the address, from the memory device using a data bus coupled to the memory device and the controller. Providing transaction metadata further includes transferring a sideband signal synchronously with the data bus and in conjunction with the address bus using a transaction metadata bus coupled to the memory device and the controller.

公开(公告)号：US20210286737A1

公开(公告)日：2021-09-16

申请号：US17337130

申请日：2021-06-02

Applicant: Micron Technology, Inc.

Inventor： Danilo Caraccio ,  Graziano Mirichigni

IPC: G06F12/14 ,  G06F21/79

Abstract: A device includes a memory. The device also includes a controller. The controller includes a register configured to store an indication of whether an ability of a received command to alter an access protection scheme of the memory is enabled. The received command may alter the access an access protection scheme of the memory responsive to the indication.

公开(公告)号：US20210200478A1

公开(公告)日：2021-07-01

申请号：US17140625

申请日：2021-01-04

Applicant: Micron Technology, Inc.

Inventor： Victor Y. Tsai ,  Danilo Caraccio ,  Daniele Balluchi ,  Neal A. Galbo ,  Robert Warren

IPC: G06F3/06

Abstract: The present disclosure includes apparatuses and methods for command queuing. A number of embodiments include receiving a queued command request at a memory system from a host, sending a command response from the memory system to the host that indicates the memory system is ready to receive a command in a command queue of the memory system, and receiving, in response to sending the command response, a command descriptor block for the command at the memory system from the host.

公开(公告)号：US10916324B2

公开(公告)日：2021-02-09

申请号：US16128113

申请日：2018-09-11

Applicant: Micron Technology, Inc.

Inventor： Paolo Amato ,  Marco Dallabora ,  Daniele Balluchi ,  Danilo Caraccio ,  Emanuele Confalonieri

IPC: G11C29/00 ,  G11C29/42 ,  G11C29/44 ,  G11C13/00 ,  G11C7/22 ,  G06F11/10 ,  G11C29/04

Abstract: An example apparatus includes a memory comprising a plurality of managed units corresponding to respective groups of resistance variable memory cells and a controller coupled to the memory. The controller is configured to cause performance of a cleaning operation on a selected group of the memory cells and generation of error correction code (ECC) parity data. The controller may be further configured to cause performance of a write operation on the selected group of cells to write an inverted state of at least one data value to the selected group of cells and write an inverted state of at least one of the ECC parity data to the selected group of cells.

公开(公告)号：US20200293211A1

公开(公告)日：2020-09-17

申请号：US16890511

申请日：2020-06-02

Applicant: Micron Technology, Inc.

Inventor： Danilo Caraccio ,  Emanuele Confalonieri ,  Marco Dallabora ,  Roberto Izzi ,  Paolo Amato ,  Daniele Balluchi ,  Luca Porzio

IPC: G06F3/06

Abstract: An example apparatus includes a hybrid memory system to couple to a host and a controller coupled to the hybrid memory system. The controller may be configured to assign a sensitivity to a command and cause the command to be selectively diverted to the hybrid memory system based, at least in part, on the assigned sensitivity.

公开(公告)号：US20200233585A1

公开(公告)日：2020-07-23

申请号：US16839721

申请日：2020-04-03

Applicant: Micron Technology, Inc.

Inventor： Emanuele Confalonieri ,  Marco Dallabora ,  Paolo Amato ,  Danilo Caraccio ,  Daniele Balluchi

IPC: G06F3/06 ,  G11C11/00 ,  G11C13/00 ,  G11C16/26

Abstract: The present disclosure includes apparatuses, methods, and systems for data relocation in hybrid memory. A number of embodiments include a memory, wherein the memory includes a first type of memory and a second type of memory, and a controller configured to identify a subset of data stored in the first type of memory to relocate to the second type of memory based, at least in part, on a frequency at which an address corresponding to the subset of data stored in the first type of memory has been accessed during program operations performed on the memory.

公开(公告)号：US10705963B2

公开(公告)日：2020-07-07

申请号：US15927530

申请日：2018-03-21

Applicant: Micron Technology, Inc.

Inventor： Danilo Caraccio ,  Emanuele Confalonieri ,  Marco Dallabora ,  Roberto Izzi ,  Paolo Amato ,  Daniele Balluchi ,  Luca Porzio

IPC: G06F3/06 ,  G06F12/0862 ,  G06F12/10

Abstract: An example apparatus comprises a hybrid memory system and a controller coupled to the hybrid memory system. The controller may be configured to cause data to be selectively stored in the hybrid memory system responsive to a determination that an exception involving the data has occurred.

公开(公告)号：US20200152267A1

公开(公告)日：2020-05-14

申请号：US16744643

申请日：2020-01-16

Applicant: Micron Technology, Inc.

Inventor： Marco Dallabora ,  Paolo Amato ,  Daniele Balluchi ,  Danilo Caraccio ,  Emanuele Confalonieri

IPC: G11C13/00 ,  G06F13/16

Abstract: The present disclosure includes apparatuses, and methods for data state synchronization. An example apparatus includes performing a write operation to store a data pattern in a group of resistance variable memory cells corresponding to a selected managed unit having a first status, updating a status of the selected managed unit from the first status to a second status responsive to performing the write operation, and providing data state synchronization for a subsequent write operation performed on the group by placing all of the variable resistance memory cells of the group in a same state prior to performing the subsequent write operation to store another data pattern in the group of resistance variable memory cells.

公开(公告)号：US10573383B2

公开(公告)日：2020-02-25

申请号：US16124222

申请日：2018-09-07

Applicant: Micron Technology, Inc.

Inventor： Marco Dallabora ,  Paolo Amato ,  Daniele Balluchi ,  Danilo Caraccio ,  Emanuele Confalonieri

IPC: G11C11/00 ,  G11C13/00

Abstract: The present disclosure includes apparatuses, and methods for data state synchronization. An example apparatus includes performing a write operation to store a data pattern in a group of resistance variable memory cells corresponding to a selected managed unit having a first status, updating a status of the selected managed unit from the first status to a second status responsive to performing the write operation, and providing data state synchronization for a subsequent write operation performed on the group by placing all of the variable resistance memory cells of the group in a same state prior to performing the subsequent write operation to store another data pattern in the group of resistance variable memory cells.