公开(公告)号：US20210272607A1

公开(公告)日：2021-09-02

申请号：US17203406

申请日：2021-03-16

Applicant: Micron Technology, Inc.

Inventor： Theodore T. Pekny ,  Victor Y. Tsai

IPC: G11C7/10 ,  G06F13/16 ,  G06F3/06 ,  G06F12/14

Abstract: Memory devices are provided that include special operating modes accessible upon receipt of a particular message from a host. One device includes a memory array, a special mode enable register, and a controller. When the controller receives a register write command to write first data into the special mode enable register and the memory device does so, the memory device operates in a first mode. When the controller receives a register write command to write second data into the special mode enable register and the memory device does so, the memory device operates in a second mode.

公开(公告)号：US20210200478A1

公开(公告)日：2021-07-01

申请号：US17140625

申请日：2021-01-04

Applicant: Micron Technology, Inc.

Inventor： Victor Y. Tsai ,  Danilo Caraccio ,  Daniele Balluchi ,  Neal A. Galbo ,  Robert Warren

IPC: G06F3/06

Abstract: The present disclosure includes apparatuses and methods for command queuing. A number of embodiments include receiving a queued command request at a memory system from a host, sending a command response from the memory system to the host that indicates the memory system is ready to receive a command in a command queue of the memory system, and receiving, in response to sending the command response, a command descriptor block for the command at the memory system from the host.

公开(公告)号：US10762003B2

公开(公告)日：2020-09-01

申请号：US16118501

申请日：2018-08-31

Applicant: Micron Technology, Inc.

Inventor： William H. Radke ,  Victor Y. Tsai ,  James Cooke ,  Neal A. Galbo ,  Peter Feeley

IPC: G06F13/16 ,  G06F13/10 ,  G06F13/38 ,  G11C7/10 ,  G11C7/22 ,  G06F3/06 ,  G06F13/42

Abstract: The present disclosure includes methods, devices, and systems for state change in systems having devices coupled in a chained configuration. A number of embodiments include a host and a number of devices coupled to the host in a chained configuration. The chained configuration includes at least one device that is not directly coupled to the host. The at least one device that is not directly coupled to the host is configured to change from a first communication state to a second communication state responsive to receipt of a command from the host.

公开(公告)号：US20190102112A1

公开(公告)日：2019-04-04

申请号：US16207453

申请日：2018-12-03

Applicant: Micron Technology, Inc.

Inventor： Victor Y. Tsai ,  Danilo Caraccio ,  Daniele Balluchi ,  Neal A. Galbo ,  Robert Warren

IPC: G06F3/06

Abstract: The present disclosure includes apparatuses and methods for command queuing. A number of embodiments include receiving a queued command request at a memory system from a host, sending a command response from the memory system to the host that indicates the memory system is ready to receive a command in a command queue of the memory system, and receiving, in response to sending the command response, a command descriptor block for the command at the memory system from the host.

公开(公告)号：US09811258B2

公开(公告)日：2017-11-07

申请号：US14557682

申请日：2014-12-02

Applicant: Micron Technology, Inc.

Inventor： Neal A. Galbo ,  Peter Feeley ,  William H. Radke ,  Victor Y. Tsai ,  Robert N. Leibowitz

IPC: G06F3/06 ,  G06F13/16

CPC classification number: G06F3/0604 ,  G06F3/0659 ,  G06F3/0683 ,  G06F13/1642

Abstract: The present disclosure includes methods for controlling host memory access with a memory device, systems, host controllers and memory devices. One embodiment for controlling host memory access with a memory device includes receiving at least one command from a host and controlling execution of the at least one command with the memory device.

公开(公告)号：US09122420B2

公开(公告)日：2015-09-01

申请号：US14231393

申请日：2014-03-31

Applicant: Micron Technology, Inc.

Inventor： Theodore T. Pekny ,  Victor Y. Tsai

IPC: G11C11/34 ,  G06F3/06 ,  G06F13/16

CPC classification number: G11C7/1021 ,  G06F3/0619 ,  G06F3/0629 ,  G06F3/0679 ,  G06F12/145 ,  G06F13/1694 ,  G06F2212/1052 ,  G11C7/1072

Abstract: A memory device includes a memory array, a special mode enable register, and a controller. When the controller receives a register write command to write first data into the special mode enable register and the memory device does so, the memory device operates in a first mode. When the controller receives a register write command to write second data into the special mode enable register and the memory device does so, the memory device operates in a second mode.

Abstract translation: 存储器件包括存储器阵列，特殊模式使能寄存器和控制器。 当控制器接收到写入第一数据到特殊模式使能寄存器并且存储器件这样做的寄存器写入命令时，存储器件以第一模式工作。 当控制器接收到寄存器写入命令以将第二数据写入特殊模式使能寄存器并且存储器件这样做时，存储器件以第二模式工作。

公开(公告)号：US20230335166A1

公开(公告)日：2023-10-19

申请号：US18134318

申请日：2023-04-13

Applicant: Micron Technology, Inc.

Inventor： Theodore T. Pekny ,  Victor Y. Tsai

IPC: G11C7/10 ,  G06F3/06 ,  G06F13/16 ,  G06F12/14 ,  G11C16/06

CPC classification number: G11C7/1021 ,  G06F3/0679 ,  G06F13/1694 ,  G06F3/0629 ,  G11C7/1072 ,  G06F12/145 ,  G11C16/06 ,  G06F3/0619 ,  G06F2212/1052

Abstract: Memory devices are provided that include special operating modes accessible upon receipt of a particular message from a host. One device includes a memory array, a special mode enable register, and a controller. When the controller receives a register write command to write first data into the special mode enable register and the memory device does so, the memory device operates in a first mode. When the controller receives a register write command to write second data into the special mode enable register and the memory device does so, the memory device operates in a second mode.

公开(公告)号：US11657857B2

公开(公告)日：2023-05-23

申请号：US17203406

申请日：2021-03-16

Applicant: Micron Technology, Inc.

Inventor： Theodore T. Pekny ,  Victor Y. Tsai

IPC: G11C7/00 ,  G11C7/10 ,  G06F13/16 ,  G11C16/06 ,  G06F3/06 ,  G06F12/14

CPC classification number: G11C7/1021 ,  G06F3/0619 ,  G06F3/0629 ,  G06F3/0679 ,  G06F12/145 ,  G06F13/1694 ,  G11C7/1072 ,  G11C16/06 ,  G06F2212/1052

Abstract: Memory devices are provided that include special operating modes accessible upon receipt of a particular message from a host. One device includes a memory array, a special mode enable register, and a controller. When the controller receives a register write command to write first data into the special mode enable register and the memory device does so, the memory device operates in a first mode. When the controller receives a register write command to write second data into the special mode enable register and the memory device does so, the memory device operates in a second mode.

公开(公告)号：US11494122B2

公开(公告)日：2022-11-08

申请号：US17140625

申请日：2021-01-04

Applicant: Micron Technology, Inc.

Inventor： Victor Y. Tsai ,  Danilo Caraccio ,  Daniele Balluchi ,  Neal A. Galbo ,  Robert Warren

IPC: G06F3/06

Abstract: The present disclosure includes apparatuses and methods for command queuing. A number of embodiments include receiving a queued command request at a memory system from a host, sending a command response from the memory system to the host that indicates the memory system is ready to receive a command in a command queue of the memory system, and receiving, in response to sending the command response, a command descriptor block for the command at the memory system from the host.

公开(公告)号：US10192591B2

公开(公告)日：2019-01-29

申请号：US16013773

申请日：2018-06-20

Applicant: Micron Technology, Inc.

Inventor： Theodore T. Pekny ,  Victor Y. Tsai

IPC: G11C7/22 ,  G11C7/10 ,  G06F13/16 ,  G06F3/06 ,  G06F12/14

Abstract: Memory devices are provided that include special operating modes accessible upon receipt of a particular message from a host. One device includes a memory array, a special mode enable register, and a controller. When the controller receives a register write command to write first data into the special mode enable register and the memory device does so, the memory device operates in a first mode. When the controller receives a register write command to write second data into the special mode enable register and the memory device does so, the memory device operates in a second mode.