公开(公告)号：US11556479B1

公开(公告)日：2023-01-17

申请号：US17397799

申请日：2021-08-09

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  David Aaron Palmer

IPC: G06F12/00 ,  G06F12/0893

Abstract: Methods, systems, and devices for cache block budgeting techniques are described. In some memory systems, a controller may configure a memory device with a cache. The cache may include a first subset of blocks configured to statically operate in a first mode and a second subset of blocks configured to dynamically switch between operating in the first mode and a second mode. A block operating in the second mode may be configured to store relatively more bits per memory cell than a block operating in the first mode. The controller may track and store, for each block of the second subset of blocks, a respective ratio of cycles performed in the first mode to cycles performed in the second mode. The controller may select a block from the second subset of blocks to switch between modes responsive to a trigger and based on the respective ratio for the block.

公开(公告)号：US11500769B2

公开(公告)日：2022-11-15

申请号：US17129373

申请日：2020-12-21

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer

IPC: G06F12/02 ,  G06F12/0891

Abstract: Methods, systems, and devices for valid data identification for garbage collection are described. In connection with writing data to a block of memory cells, a memory system may identify a portion of a logical address space that includes a logical address for the data. The memory system may set a bit of a bitmap, which may indicate that the block includes data having a logical address within a portion of the logical address space corresponding to the bit. The logical address space may be divided into any quantity of portions, each corresponding to a different subset of a logical-to-physical (L2P) table, and the bitmap may include any quantity of corresponding bits. To perform garbage collection on the block, the bitmap may be used to identify one or more subsets of the L2P table to evaluate to determine whether different sets of data within the block are valid or invalid.

公开(公告)号：US20220317900A1

公开(公告)日：2022-10-06

申请号：US17725119

申请日：2022-04-20

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  David Aaron Palmer

IPC: G06F3/06

Abstract: Methods, systems, and devices for memory device with enhanced data reliability capabilities are described. For a write operation, a memory device may receive a write command from a host device indicating a first set of data. The memory device may determine to operate in first mode of operation associated with a reliability above a threshold and generate a second set of data to store with the first set of data based on operating in the first mode of operation. For a read operation, the memory device may identify that a read command received from a host device is associated with the first mode of operation. Based on operating in the first mode of operation, the memory device may select one or more reference thresholds (e.g., a subset of reference thresholds) to retrieve the first set of data and transmit the first set of data to the host device.

公开(公告)号：US20220214818A1

公开(公告)日：2022-07-07

申请号：US17701356

申请日：2022-03-22

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer

IPC: G06F3/06

Abstract: Apparatus and methods are disclosed, including a controller circuit, a volatile memory, a non-volatile memory, and a reset circuit, where the reset circuit is configured to receive a reset signal from a host device and actuate a timer circuit. The timer circuit, where the timer circuit is configured to cause a storage device to reset after a threshold time period. The reset circuit is further configured to actuate the controller circuit to write data stored in the volatile memory to the non-volatile memory before the storage device is reset.

公开(公告)号：US11294585B2

公开(公告)日：2022-04-05

申请号：US17129087

申请日：2020-12-21

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer ,  Sean L. Manion ,  Jonathan Scott Parry ,  Stephen Hanna ,  Qing Liang ,  Nadav Grosz ,  Christian M. Gyllenskog ,  Kulachet Tanpairoj

IPC: G06F3/06 ,  G06F12/02

Abstract: Apparatus and methods are disclosed, including using a memory controller to partition a memory array into a first portion and a second portion, the first portion and second portion having non-overlapping logical block addressing (LBA) ranges. The memory controller assigns a first granularity of a first logical-to-physical (L2P) mapping table entry for the first portion of the memory array designated for a first usage, and a second granularity of a second L2P mapping table entry for the second portion of the memory array designated for a second usage, where the second granularity is not equal to the first granularity. The memory controller stores the first granularity and the second granularity in the memory array, and stores at least a portion of the first L2P mapping table entry and the second L2P mapping table entry in an L2P cache of the memory controller.

公开(公告)号：US11287986B2

公开(公告)日：2022-03-29

申请号：US16236785

申请日：2018-12-31

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer

IPC: G06F3/06

Abstract: Apparatus and methods are disclosed, including a controller circuit, a volatile memory, a non-volatile memory, and a reset circuit, where the reset circuit is configured to receive a reset signal from a host device and actuate a timer circuit. The timer circuit, where the timer circuit is configured to cause a storage device to reset after a threshold time period. The reset circuit is further configured to actuate the controller circuit to write data stored in the volatile memory to the non-volatile memory before the storage device is reset.

公开(公告)号：US20220083263A1

公开(公告)日：2022-03-17

申请号：US17532020

申请日：2021-11-22

Applicant: Micron Technology, Inc.

Inventor： Nadav Grosz ,  David Aaron Palmer

IPC: G06F3/06

Abstract: Devices and techniques for generating a response to a host with a memory device are provided. A first command from a host can be executed. A status for the first command can he determined. An inquiry from the host about a second command can be received after execution of the first command has begun. A response can be made to the inquiry that includes information about the second command and the status for the first command.

公开(公告)号：US11263124B2

公开(公告)日：2022-03-01

申请号：US16054072

申请日：2018-08-03

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer

IPC: G06F12/02 ,  G06F12/0873 ,  G06F12/0871

Abstract: Devices and techniques are disclosed herein for verifying host generated physical addresses at a memory device during a host-resident FTL mode of operation to ameliorate erroneous or potentially malicious access to the memory device.

公开(公告)号：US20220057948A1

公开(公告)日：2022-02-24

申请号：US17000015

申请日：2020-08-21

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  David Aaron Palmer

IPC: G06F3/06

Abstract: Methods, systems, and devices for memory device with enhanced data reliability capabilities are described. For a write operation, a memory device may receive a write command from a host device indicating a first set of data. The memory device may determine to operate in first mode of operation associated with a reliability above a threshold and generate a second set of data to store with the first set of data based on operating in the first mode of operation. For a read operation, the memory device may identify that a read command received from a host device is associated with the first mode of operation. Based on operating in the first mode of operation, the memory device may select one or more reference thresholds (e.g., a subset of reference thresholds) to retrieve the first set of data and transmit the first set of data to the host device.

公开(公告)号：US11237617B2

公开(公告)日：2022-02-01

申请号：US16293295

申请日：2019-03-05

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer

IPC: G06F1/32 ,  G06F3/06 ,  G06F9/48 ,  G06F9/54 ,  G06F9/38 ,  G06F1/3234 ,  G06F1/3225

Abstract: Devices and techniques for arbitrating operation of memory devices in a managed NAND memory system to conform the operation to a power budget. In an example, a method can include receiving an operation change indication for a NAND memory operation at power management circuitry of a NAND memory system, and summing a power credit to a value of a first register associated with the operation change indication to provide an indication of instantaneous power consumption of the NAND memory system as the value of the first register.