公开(公告)号：US20080225622A1

公开(公告)日：2008-09-18

申请号：US12125733

申请日：2008-05-22

申请人： Hideto Hidaka

发明人： Hideto Hidaka

IPC分类号： G11C8/00

CPC分类号： G11C11/005

摘要： A thin film magnetic memory includes a size-variable Read Only Memory (ROM) region and a size-variable Random Access Memory (RAM) coupled to different ports for parallel access to the ports, respectively. A memory system allowing fast and efficient data transfer can be achieved.

摘要翻译： 薄膜磁存储器包括大小可变只读存储器（ROM）区域和耦合到不同端口的大小可变随机存取存储器（RAM），用于并行地访问端口。 可以实现快速高效的数据传输的存储器系统。

公开(公告)号：US20080122479A1

公开(公告)日：2008-05-29

申请号：US12010427

申请日：2008-01-24

申请人： Hideto Hidaka

发明人： Hideto Hidaka

IPC分类号： H03K17/16

CPC分类号： G11C5/147 ,  H01L27/0922 ,  H03K19/0016

摘要： A logic gate is constructed of an insulated gate field effect transistor (MIS transistor) having a thin gate insulation film. An operation power supply line to the logic gate is provided with an MIS transistor having a thick gate insulation film for switching the supply and stop of an operation power source voltage. A voltage of the gate of the power source switching transistor is made changing in an amplitude greater than an amplitude of an input and an output signal to the logic gate. Current consumption in a semiconductor device configured of MIS transistor of a thin gate insulation film can be reduced and an power source voltage thereof can be stabilized.

摘要翻译： 逻辑门由具有薄栅绝缘膜的绝缘栅场效应晶体管（MIS晶体管）构成。 提供到逻辑门的操作电源线设置有具有用于切换供电和停止操作电源电压的厚栅极绝缘膜的MIS晶体管。 使电源开关晶体管的栅极的电压以大于输入的幅度和输出信号的幅度变化为逻辑门。 可以减小由薄栅绝缘膜的MIS晶体管构成的半导体器件中的电流消耗，并且其电源电压可以稳定。

公开(公告)号：US07355455B2

公开(公告)日：2008-04-08

申请号：US11369852

申请日：2006-03-08

申请人： Hideto Hidaka

发明人： Hideto Hidaka

IPC分类号： H03K19/20 ,  G05F1/10

CPC分类号： G11C5/147 ,  H01L27/0922 ,  H03K19/0016

摘要： A logic gate is constructed of an insulated gate field effect transistor (MIS transistor) having a thin gate insulation film. An operation power supply line to the logic gate is provided with an MIS transistor having a thick gate insulation film for switching the supply and stop of an operation power source voltage. A voltage of the gate of the power source switching transistor is made changing in an amplitude greater than an amplitude of an input and an output signal to the logic gate. Current consumption in a semiconductor device configured of MIS transistor of a thin gate insulation film can be reduced and an power source voltage thereof can be stabilized.

摘要翻译： 逻辑门由具有薄栅绝缘膜的绝缘栅场效应晶体管（MIS晶体管）构成。 提供到逻辑门的操作电源线设置有具有用于切换供电和停止操作电源电压的厚栅极绝缘膜的MIS晶体管。 使电源开关晶体管的栅极的电压以大于输入的幅度和输出信号的幅度变化为逻辑门。 可以减小由薄栅绝缘膜的MIS晶体管构成的半导体器件中的电流消耗，并且其电源电压可以稳定。

公开(公告)号：US20080037315A1

公开(公告)日：2008-02-14

申请号：US11907168

申请日：2007-10-10

申请人： Hideto Hidaka

发明人： Hideto Hidaka

IPC分类号： G11C11/00

CPC分类号： G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675

摘要： An end of a selected bit line in a selected column is electrically coupled to an end of a corresponding current return line by one of first and second write column select gates, which are selectively turned on in response to results of column selection. A data write circuit sets the other end of the selected bit line and the other end of the current return line to one and the other of a power supply voltage and a ground voltage in accordance with a level of write data via one of first and second data buses and an inverted data bus, respectively.

摘要翻译： 所选列中的所选位线的一端通过第一和第二写列选择栅中的一个电耦合到对应的电流返回线的一端，这些选择栅根据列选择的结果选择性地导通。 数据写入电路根据写入数据的电平，将所选位线的另一端和当前返回线的另一端设置为电源电压和接地电压的另一端，经由第一和第二 数据总线和反相数据总线。

公开(公告)号：US07313017B2

公开(公告)日：2007-12-25

申请号：US11374063

申请日：2006-03-14

申请人： Tsukasa Ooishi ,  Hideto Hidaka

发明人： Tsukasa Ooishi ,  Hideto Hidaka

IPC分类号： G11C11/14

CPC分类号： G11C7/1051 ,  G11C7/06 ,  G11C11/16 ,  G11C29/02 ,  G11C29/026 ,  G11C29/028

摘要： In read operation, a current from a current supply transistor flows through a selected memory cell and a data line. Moreover, a bias magnetic field having such a level that does not destroy storage data is applied to the selected memory cell. By application of the bias magnetic field, an electric resistance of the selected memory cell changes in the positive or negative direction depending on the storage data level. A sense amplifier amplifies the difference between voltages on the data line before and after the change in electric resistance of the selected memory cell. Data is thus read from the selected memory cell by merely accessing the selected memory cell. Moreover, since the data line and the sense amplifier are insulated from each other by a capacitor, the sense amplifier can be operated in an optimal input voltage range regardless of magnetization characteristics of the memory cells.

摘要翻译： 在读取操作中，来自电流供给晶体管的电流流过选定的存储单元和数据线。 此外，具有不破坏存储数据的等级的偏置磁场被施加到所选存储单元。 通过施加偏置磁场，所选择的存储单元的电阻根据存储数据电平在正或负方向上变化。 读出放大器放大所选存储单元的电阻变化前后的数据线上的电压差。 因此，通过仅访问所选择的存储器单元，从所选择的存储器单元读取数据。 此外，由于数据线和读出放大器通过电容器彼此绝缘，所以无论存储器单元的磁化特性如何，读出放大器都可以在最佳输入电压范围内工作。

公开(公告)号：US07295465B2

公开(公告)日：2007-11-13

申请号：US11374062

申请日：2006-03-14

申请人： Hiroaki Tanizaki ,  Hideto Hidaka ,  Tsukasa Ooishi

发明人： Hiroaki Tanizaki ,  Hideto Hidaka ,  Tsukasa Ooishi

IPC分类号： G11C11/14

CPC分类号： G11C11/15 ,  G11C11/16

摘要： During data reading, a sense enable signal is activated to start charging of a data line prior to formation of a current path including the data line and a selected memory cell in accordance with row and column selecting operations. Charging of the data line is completed early so that it is possible to reduce a time required from start of the data reading to such a state that a passing current difference between the data lines reaches a level corresponding to storage data of the selected memory cell, and the data reading can be performed fast.

摘要翻译： 在数据读取期间，根据行和列选择操作，激活感测使能信号以在形成包括数据线的当前路径和所选择的存储器单元之前开始数据线的充电。 早期完成数据线的充电，从而可以将开始数据读取所需的时间减少到数据线之间的通过电流差达到对应于所选存储单元的存储数据的电平的状态， 并且可以快速执行数据读取。

公开(公告)号：US07250796B2

公开(公告)日：2007-07-31

申请号：US11223937

申请日：2005-09-13

申请人： Hideto Hidaka ,  Masakazu Hirose

发明人： Hideto Hidaka ,  Masakazu Hirose

IPC分类号： H03K21/18

CPC分类号： H03K19/00361

摘要： A data output drive transistor is rendered conductive when the potential of an internal node attains an H level, whereby an output node is discharged to the level of ground potential. When the drive transistor is turned on, the output node is discharged to the level of ground potential at high speed. This drive transistor is turned on for a predetermined time period when output of a high level data is completed, whereby the output node is discharged to the level of the ground potential for a predetermined time period. As a result, the potential of the output node is lowered from a high level to an intermediate level, so that the amplitude of a subsequent output signal is reduced. An output circuit that can effectively prevent generation of ringing with no increase in the access time is provided. A countermeasure is provided to suppress a ringing at output node which drives the output node at high speed when the output node potential attains a potential at which no ringing is caused. A stable output signal is provided at high speed.

摘要翻译： 当内部节点的电位达到H电平时，数据输出驱动晶体管导通，从而将输出节点放电到地电位。 当驱动晶体管导通时，输出节点以高速放电到地电位。 当高电平数据的输出完成时，该驱动晶体管导通预定时间段，由此输出节点在预定时间段内被放电到地电位的电平。 结果，输出节点的电位从高电平降低到中间电平，使得后续输出信号的幅度减小。 提供了可以有效地防止产生振铃而不增加访问时间的输出电路。 提供了一种对策，用于当输出节点电位达到不产生振铃的电位时，抑制在输出节点处高速驱动输出节点的振铃。 高速提供稳定的输出信号。

公开(公告)号：US20070159870A1

公开(公告)日：2007-07-12

申请号：US11645610

申请日：2006-12-27

申请人： Hiroaki Tanizaki ,  Takaharu Tsuji ,  Yasumitsu Murai ,  Hideto Hidaka

发明人： Hiroaki Tanizaki ,  Takaharu Tsuji ,  Yasumitsu Murai ,  Hideto Hidaka

IPC分类号： G11C11/00

CPC分类号： G11C11/16 ,  G11C11/5607 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2213/31 ,  G11C2213/79

摘要： Source lines for a spin injection magnetic memory cell are arranged parallel to word lines for executing writing/reading of data multiple bits at a time. In a write operation, a source line potential changes in a predetermined sequence such that the source line commonly connected to a plurality of selected memory cells is set to pass a current only in one direction in each stage of the operation sequence. For the data write sequence, a current is caused to flow through memory cells according to write data sequentially, or the memory cell has a resistance state set to an initial resistance state before writing, and then changed to a state according to the write data Fast writing can be achieved in the magnetic memory without increasing a memory cell layout area.

摘要翻译： 自旋注入磁存储单元的源极线与字线平行地布置，用于一次执行数据多位读写。 在写入操作中，源极线电位以预定的顺序改变，使得共同连接到多个选择的存储器单元的源极线被设置为仅在操作序列的每个阶段中在一个方向上传递电流。 对于数据写入序列，根据写入数据顺序地使电流流过存储器单元，或者存储单元在写入之前具有设置为初始电阻状态的电阻状态，然后根据写入数据快速变为状态 可以在磁存储器中实现写入，而不增加存储单元布局区域。

公开(公告)号：US20070091670A1

公开(公告)日：2007-04-26

申请号：US11580942

申请日：2006-10-16

申请人： Hideto Hidaka

发明人： Hideto Hidaka

IPC分类号： G11C11/00 ,  G11C11/14 ,  G11C11/15 ,  G11C5/02 ,  G11C5/08

CPC分类号： G11C5/025 ,  B82Y10/00 ,  G11C11/1653 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693 ,  H01L27/228

摘要： Read word lines and write word lines are provided corresponding to the respective MTJ (Magnetic Tunnel Junction) memory cell rows, and bit lines and reference voltage lines are provided corresponding to the respective MTJ memory cell columns. Adjacent MTJ memory cells share at least one of these signal lines. As a result, the pitches of signal lines provided in the entire memory array can be widened. Thus, the MTJ memory cells can be efficiently arranged, achieving improved integration of the memory array.

摘要翻译： 对应于相应的MTJ（磁隧道结）存储单元行提供读字线和写字线，并且对应于相应的MTJ存储单元列提供位线和参考电压线。 相邻的MTJ存储器单元共享这些信号线中的至少一个。 结果，可以扩大设置在整个存储器阵列中的信号线的间距。 因此，可以有效地布置MTJ存储器单元，实现存储器阵列的改进的集成。

公开(公告)号：US20070076472A1

公开(公告)日：2007-04-05

申请号：US11607893

申请日：2006-12-04

申请人： Hideto Hidaka

发明人： Hideto Hidaka

IPC分类号： G11C11/14

CPC分类号： G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675

摘要： An end of a selected bit line in a selected column is electrically coupled to an end of a corresponding current return line by one of first and second write column select gates, which are selectively turned on in response to results of column selection. A data write circuit sets the other end of the selected bit line and the other end of the current return line to one and the other of a power supply voltage and a ground voltage in accordance with a level of write data via one of first and second data buses and an inverted data bus, respectively.