公开(公告)号：US09128152B2

公开(公告)日：2015-09-08

申请号：US14456125

申请日：2014-08-11

Applicant: Texas Instruments Incorporated

Inventor： Lee D. Whetsel

IPC: G01R31/3177 ,  G01R31/302 ,  G01R31/3185 ,  G01R31/28

CPC classification number: G01R31/31713 ,  G01R31/2815 ,  G01R31/2851 ,  G01R31/2884 ,  G01R31/3025 ,  G01R31/31703 ,  G01R31/31725 ,  G01R31/31727 ,  G01R31/3177 ,  G01R31/318558

Abstract: The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices (504), only reduced pin JTAG devices (506), or a mixture of both full pin and reduced pin JTAG devices. The access is accomplished using a single interface (502) between the substrate (408) and a JTAG controller (404). The access interface may be a wired interface or a wireless interface and may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.

Abstract translation: 本公开描述了用于访问基板上的设备的过程和设备。 衬底可以仅包括全引脚JTAG器件（504），只有减少的引脚JTAG器件（506），或者是完全引脚和降低引脚JTAG器件的混合。 使用在基板（408）和JTAG控制器（404）之间的单个接口（502）来实现访问。 访问接口可以是有线接口或无线接口，并且可以用于基于JTAG的设备测试，调试，编程或其他类型的基于JTAG的操作。

公开(公告)号：US20150247897A1

公开(公告)日：2015-09-03

申请号：US14698298

申请日：2015-04-28

Applicant: Texas Instruments Incorporated

Inventor： Lee D. Whetsel

IPC: G01R31/3177

CPC classification number: G01R31/3177 ,  G01R31/31723 ,  G01R31/31727 ,  G01R31/318555 ,  G01R31/318572

Abstract: The disclosure describes a novel method and apparatus for making device TAPs addressable to allow device TAPs to be accessed in a parallel arrangement without the need for having a unique TMS signal for each device TAP in the arrangement. According to the disclosure, device TAPs are addressed by inputting an address on the TDI input of devices on the falling edge of TCK. An address circuit within the device is associated with the device's TAP and responds to the address input to either enable or disable access of the device's TAP.

公开(公告)号：US09121903B2

公开(公告)日：2015-09-01

申请号：US14547781

申请日：2014-11-19

Applicant: Texas Instruments Incorporated

Inventor： Lee D. Whetsel

IPC: G01R31/28 ,  G01R31/3177 ,  G01R31/3185

CPC classification number: G01R31/3177 ,  G01R31/318544 ,  G01R31/31855 ,  G01R31/318555 ,  G01R31/318575

Abstract: Functional circuits and cores of circuits are tested on integrated circuits using scan paths. Using parallel scan distributor and collector circuits for these scan paths improves test access of circuits and cores embedded within ICs and reduces the IC's power consumption during scan testing. A controller for the distributor and collector circuits includes a test control register, a test control state machine and a multiplexer. These test circuits can be connected in a hierarchy or in parallel. A conventional test access port or TAP can be modified to work with the disclosed test circuits.

Abstract translation: 功能电路和电路核心使用扫描路径在集成电路上进行测试。 为这些扫描路径使用并行扫描分配器和集电极电路可以改善IC内部电路和内核的测试访问，并降低了扫描测试期间的IC功耗。 用于分配器和集电极电路的控制器包括测试控制寄存器，测试控制状态机和多路复用器。 这些测试电路可以以层次结构或并行连接。 传统的测试访问端口或TAP可以被修改为与公开的测试电路一起工作。

公开(公告)号：US20150241513A1

公开(公告)日：2015-08-27

申请号：US14707794

申请日：2015-05-08

Applicant: Texas Instruments Incorporated

Inventor： Lee D. Whetsel

IPC: G01R31/3177

CPC classification number: G01R31/31723 ,  G01R31/2851 ,  G01R31/3172 ,  G01R31/31724 ,  G01R31/3173 ,  G01R31/3177 ,  G01R31/318563 ,  G01R31/318575

Abstract: A scan test architecture facilitates low power testing of semiconductor circuits by selectively dividing the serial scan paths into shorter sections. Multiplexers between the sections control connecting the sections into longer or shorted paths. Select and enable signals control the operation of the scan path sections. The output of each scan path passes through a multiplexer to compare circuits on the semiconductor substrate. The compare circuits also receive expected data and mask data. The compare circuits provide a fail flag output from the semiconductor substrate.

Abstract translation: 扫描测试架构通过将串行扫描路径选择性地分成较短的部分来促进半导体电路的低功率测试。 部分之间的多路复用器控制将部分连接到更长或短路的路径。 选择并启用信号控制扫描路径部分的操作。 每个扫描路径的输出通过多路复用器来比较半导体衬底上的电路。 比较电路还接收预期数据和掩模数据。 比较电路提供从半导体衬底输出的故障标志。

公开(公告)号：US09116208B2

公开(公告)日：2015-08-25

申请号：US14531459

申请日：2014-11-03

Applicant: Texas Instruments Incorporated

Inventor： Lee D. Whetsel

IPC: G01R31/28 ,  G01R31/3177 ,  G01R31/3185 ,  G06F11/26 ,  G06F11/34

CPC classification number: G01R31/31723 ,  G01R31/31722 ,  G01R31/31725 ,  G01R31/31727 ,  G01R31/3177 ,  G01R31/318572 ,  G06F11/261 ,  G06F11/267 ,  G06F11/27 ,  G06F11/3466

Abstract: An address and command port interface selectively enables JTAG TAP domain operations and Trace domain operations within an IC. The port carries TMS and TDI input and TDO output on a single pin and receives a clock signal on a separate pin. The addressable two pin interface loads and updates instructions and data to the TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller. A data and clock signal interface between a controller and multiple target devices provides for each target device to be individually addressed and commanded to perform a JTAG or Trace operation.

Abstract translation: 地址和命令端口接口选择性地启用IC内的JTAG TAP域操作和跟踪域操作。 端口在单个引脚上承载TMS和TDI输入和TDO输出，并在单独的引脚上接收时钟信号。 可寻址的两个引脚接口将指令和数据加载并更新到IC内的TAP域。 多个IC中的指令或数据更新操作同时发生。 过程使用数据帧将数据从寻址的目标设备发送到控制器，每个数据帧包括报头位和数据位。 标头位的逻辑电平用于启动，继续和停止向控制器传输数据。 控制器和多个目标设备之间的数据和时钟信号接口提供每个目标设备被单独寻址并命令执行JTAG或跟踪操作。

公开(公告)号：US20150234009A1

公开(公告)日：2015-08-20

申请号：US14700963

申请日：2015-04-30

Applicant: Texas Instruments Incorporated

Inventor： Lee D. Whetsel

IPC: G01R31/3177

CPC classification number: G01R31/3177 ,  G01R31/31715 ,  G01R31/3172 ,  G01R31/31725 ,  G01R31/318547

Abstract: The disclosure describes novel methods and apparatuses for controlling a device's TCA circuit when the device exists in a JTAG daisy-chain arrangement with other devices. The methods and apparatuses allow the TCA test pattern set used during device manufacturing to be reused when the device is placed in a JTAG daisy-chain arrangement with other devices, such as in a customers system using the device. Additional embodiments are also provided and described in the disclosure.

Abstract translation: 本公开描述了当设备以与其他设备的JTAG菊花链配置存在时用于控制设备的TCA电路的新颖的方法和设备。 当设备与其他设备（例如在使用该设备的客户系统中）放置在JTAG菊花链配置中时，这些方法和设备允许在设备制造期间使用的TCA测试模式集被重用。 在本公开中还提供和描述了另外的实施例。

公开(公告)号：US20150226798A1

公开(公告)日：2015-08-13

申请号：US14691016

申请日：2015-04-20

Applicant: Texas Instruments Incorporated

Inventor： Lee D. Whetsel

IPC: G01R31/3177

CPC classification number: G01R31/3177 ,  G01R31/318536

Abstract: An integrated circuit or circuit board includes functional circuitry and a scan path. The scan path includes a test data input lead, a test data output lead, a multiplexer, and scan cells. A dedicated scan cell has a functional data output separate from a test data output. Shared scan cells each have a combined output for functional data and test data. The shared scan cells are coupled in series. The test data input of the first shared scan cell is connected to the test data output of the dedicated scan cell. The combined output of one shared scan cell is coupled to the test data input lead of another shared scan cell. The multiplexer has an input coupled to the test data output, an input connected to the combined output lead of the last shared scan cell in the series, and an output connected in the scan path.

公开(公告)号：US09103885B2

公开(公告)日：2015-08-11

申请号：US14494092

申请日：2014-09-23

Applicant: Texas Instruments Incorporated

Inventor： Lee D. Whetsel ,  Alan Hales

IPC: H01L23/58 ,  G01R31/26 ,  G01R31/3185 ,  G01R31/319 ,  G01R1/073

CPC classification number: G01R31/3177 ,  G01R1/07342 ,  G01R31/318536 ,  G01R31/318541 ,  G01R31/318544 ,  G01R31/318547 ,  G01R31/318555 ,  G01R31/318558 ,  G01R31/318563 ,  G01R31/318566 ,  G01R31/318572 ,  G01R31/31924 ,  G01R31/31926

Abstract: Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible.

Abstract translation: 位于半导体管芯上的测试电路使得测试仪能够通过将激励和响应模式输入到多个管芯/ IC来并行地测试多个管芯/ IC。 来自测试器的响应模式与待比较的芯片/ IC的输出响应一起输入到测试电路。 还公开了使用响应信号编码方案，其中测试者使用每个测试电路的单个信号向测试电路发送响应测试命令，以执行：（1）比较管芯/ IC输出与期望的逻辑高（ 2）比较管芯/ IC输出与预期逻辑低电平，以及（3）掩模比较操作。 信号编码方案的使用允许对芯片和IC进行功能测试，因为每个管芯/ IC输出所需的所有响应测试命令（即1-3）都可以仅使用单个测试仪信号连接传输到每个管芯/ IC输出 芯片/ IC输出。 除功能测试外，还可以对芯片和IC进行扫描测试。

公开(公告)号：US20150177323A1

公开(公告)日：2015-06-25

申请号：US14636892

申请日：2015-03-03

Applicant: Texas Instruments Incorporated

Inventor： Lee D. Whetsel

IPC: G01R31/3177

CPC classification number: G01R31/31723 ,  G01R31/31725 ,  G01R31/31727 ,  G01R31/3177 ,  G01R31/318552 ,  G01R31/318566 ,  G01R31/318594

Abstract: The disclosure describes a novel method and apparatus for providing expected data, mask data, and control signals to scan test architectures within a device using the falling edge of a test/scan clock. The signals are provided on device leads that are also used to provide signals to scan test architectures using the rising edge of the test/scan clock. According to the disclosure, device test leads serve to input different test signals on the rising and falling edge of the test/scan clock which reduces the number of interconnects between a tester and the device under test.

公开(公告)号：US20150160295A1

公开(公告)日：2015-06-11

申请号：US14625378

申请日：2015-02-18

Applicant: Texas Instruments Incorporated

Inventor： Lee D. Whetsel

IPC: G01R31/3177

CPC classification number: G01R31/3177 ,  G01R31/31723 ,  G01R31/31725 ,  G01R31/31727 ,  G01R31/318533

Abstract: The disclosure describes a novel method and apparatuses for allowing a controller to select and access different types of access ports in a device. The selecting and accessing of the access ports is achieved using only the dedicated TDI, TMS, TCK, and TDO signal terminals of the device. The selecting and accessing of device access ports can be achieved when a single device is connected to the controller, when multiple devices are placed in a daisy-chain arrangement and connected to the controller, or when multiple devices are placed in a addressable parallel arrangement and connected to the controller. Additional embodiments are also provided and described in the disclosure.

Abstract translation: 本公开描述了一种用于允许控制器选择和访问设备中的不同类型的接入端口的新颖方法和装置。 访问端口的选择和访问仅使用设备的专用TDI，TMS，TCK和TDO信号终端来实现。 当单个设备连接到控制器时，当多个设备以菊花链布置并连接到控制器时，或者当多个设备被放置在可寻址的并行布置中时，可以实现设备访问端口的选择和访问，并且 连接到控制器。 在本公开中还提供和描述了另外的实施例。