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    ORDER-RELATION ANALYZING APPARATUS, METHOD, AND COMPUTER PROGRAM PRODUCT THEREOF
    111.
    发明申请
    ORDER-RELATION ANALYZING APPARATUS, METHOD, AND COMPUTER PROGRAM PRODUCT THEREOF 有权
    订单关系分析设备，方法和计算机程序产品

    公开(公告)号：US20090019451A1

    公开(公告)日：2009-01-15

    申请号：US12050685

    申请日：2008-03-18

    申请人： Hidenori Matsuzaki ,  Tatsuya Mori ,  Shigehiro Asano

    发明人： Hidenori Matsuzaki ,  Tatsuya Mori ,  Shigehiro Asano

    IPC分类号： G06F9/46

    CPC分类号： G06F11/3604

    摘要： An order-relation analyzing apparatus collects assigned destination processor information, a synchronization process order and synchronization information, determines a corresponding element associated with a program among a plurality of elements indicating an ordinal value of the program based on the assigned destination processor information, when an execution of the program is started, and calculates the ordinal value indicated by the corresponding element for each segment based on the synchronization information, when the synchronization process occurs while executing the program. When a first corresponding element associated with a second program, of which the execution starts after the execution of a first program associated with the first corresponding element finishes, is determined, the ordinal value of the second program is calculated by calculating the ordinal value indicated by the first corresponding element.

    摘要翻译： 订单关系分析装置收集分配的目的地处理器信息，同步处理顺序和同步信息，在基于分配的目的地处理器信息指示程序的序数值的多个元素中确定与程序相关联的对应元素，当 开始程序的执行，并且当执行程序时发生同步处理时，基于同步信息计算由每个段的相应元素指示的序数值。 当与执行与第一对应元件相关联的第一程序的执行开始的第二程序相关联的第一对应元件被确定时，通过计算第二程序的序数值来计算第二程序的顺序值， 第一个对应的元素。

    SEMICONDUCTOR DEVICE
    112.
    发明申请
    SEMICONDUCTOR DEVICE 失效
    半导体器件

    公开(公告)号：US20080244240A1

    公开(公告)日：2008-10-02

    申请号：US12050899

    申请日：2008-03-18

    申请人： Takashi Yoshikawa ,  Shigehiro Asano

    发明人： Takashi Yoshikawa ,  Shigehiro Asano

    IPC分类号： G06F9/302

    CPC分类号： G06F9/3001 ,  G06F9/3867 ,  G06F9/3879 ,  G06F15/7832 ,  Y02D10/12 ,  Y02D10/13

    摘要： A semiconductor device includes a first arithmetic engine which executes a first arithmetic process in every cycle and outputs first data representing the result of the first arithmetic process and a first valid signal representing a first or second value in every cycle, and a second arithmetic engine which executes a second arithmetic process in every cycle and outputs second data representing the result of the second arithmetic process and a second valid signal representing the first or second value in every cycle. The device also includes an inter-arithmetic-engine buffer which is used to exchange the first data and the second data between the first and second arithmetic engines, enables write of the first or second data if the first or second valid signal indicates the first value, and inhibits write of the first or second data if the first or second valid signal indicates the second value.

    摘要翻译： 半导体器件包括：第一运算引擎，其在每个周期中执行第一运算处理，并且输出表示第一运算处理结果的第一数据和表示每个周期中的第一或第二值的第一有效信号;以及第二运算引擎， 在每个周期中执行第二运算处理，并且在每个周期中输出表示第二运算处理结果的第二数据和表示第一或第二值的第二有效信号。 该装置还包括一个算术引擎缓冲器，用于在第一和第二算术引擎之间交换第一数据和第二数据，如果第一或第二有效信号指示第一值，则能够写入第一或第二数据 并且如果第一或第二有效信号指示第二值，则禁止写入第一或第二数据。

    Systems and Methods for Reducing Data Storage in Devices Using Multi-Phase Data Transactions
    113.
    发明申请
    Systems and Methods for Reducing Data Storage in Devices Using Multi-Phase Data Transactions 有权
    使用多阶段数据交易减少设备中的数据存储的系统和方法

    公开(公告)号：US20070288672A1

    公开(公告)日：2007-12-13

    申请号：US11422646

    申请日：2006-06-07

    申请人： Shigehiro Asano ,  Thuong Truong

    发明人： Shigehiro Asano ,  Thuong Truong

    IPC分类号： G06F13/00 ,  G06F1/12

    CPC分类号： G06F13/42

    摘要： Systems and methods for enforcing in-order execution of commands sent from a master device to a slave device, where it is not necessary to provide a data buffer to store data associated with commands that are delayed to enforce in-order execution. In one embodiment, when a slave receives an execution synchronization command from a master, it determines whether its command queue contains unissued commands associated with master. If the command queue contains unissued commands, the slave issues a retry responsive to the execution synchronization command. If the command queue does not contain unissued commands, the slave issues an acknowledgment responsive to the execution synchronization command. The master will retry the execution synchronization command until the previous commands have been completed. Because the slave does not queue up any commands that would be delayed by the execution synchronization command, it does not have to provide space to store any associated data.

    摘要翻译： 用于执行从主设备发送到从设备的命令的按顺序执行的系统和方法，其中不需要提供数据缓冲器来存储与被延迟以强制执行顺序执行的命令相关联的数据。 在一个实施例中，当从机从主机接收到执行同步命令时，它确定其命令队列是否包含与主机相关联的未发出的命令。 如果命令队列包含未发出的命令，则从站会根据执行同步命令发出重试。 如果命令队列不包含未发出的命令，则从机将响应于执行同步命令发出确认。 主机将重试执行同步命令，直到之前的命令完成。 因为从站不排队将被执行同步命令延迟的任何命令，所以它不必提供存储任何关联数据的空间。

    System and method for facilitating communication between devices on a bus using tags
    114.
    发明授权
    System and method for facilitating communication between devices on a bus using tags 失效
    使用标签促进总线上设备之间通信的系统和方法

    公开(公告)号：US07203780B2

    公开(公告)日：2007-04-10

    申请号：US11063174

    申请日：2005-02-22

    申请人： Shigehiro Asano ,  Tsutomu Ishii

    发明人： Shigehiro Asano ,  Tsutomu Ishii

    IPC分类号： G00F13/00

    CPC分类号： G06F13/4221

    摘要： Systems and methods for enabling a slave device to generate a tag that is an index into a buffer where the slave device stores information related to an active transaction such as a write command received by a master device. The tag is sent to the master device with a reply (such as a response to a write command received from the master device), the master device returns the tag with the data to be written to the slave device. The slave device can efficiently associate the received data with the previously sent write command by retrieving the command from the buffer using the tag as an index into the buffer. Additional hardware such as a content-addressable memory unit is not required to make the association.

    摘要翻译： 用于使从设备能够生成作为缓存器的索引的标签的系统和方法，其中从设备存储与主设备接收的诸如写命令之类的活动事务相关的信息。 标签通过回复（例如对从主设备接收到的写命令的响应）发送到主设备，主设备将具有要写入从设备的数据的标签返回。 从设备可以通过使用标签作为缓冲器的索引从缓冲器中检索命令来有效地将接收到的数据与先前发送的写入命令相关联。 不需要诸如内容寻址存储器单元的附加硬件来进行关联。

    Back-off timing mechanism
    115.
    发明申请
    Back-off timing mechanism 有权
    退货定时机制

    公开(公告)号：US20060230205A1

    公开(公告)日：2006-10-12

    申请号：US11100081

    申请日：2005-04-06

    申请人： Shigehiro Asano ,  Tsutomu Ishli

    发明人： Shigehiro Asano ,  Tsutomu Ishli

    IPC分类号： G06F13/00

    CPC分类号： G06F13/4009

    摘要： Systems and methods for implementing back-off timing for retries of commands sent from a master device to a slave device over a split-transaction bus. One embodiment includes a buffer having entries for storing each pending command and associated information, including a number of retries of the command and a static pseudorandom timer expiration value. The timer expiration value of each entry is compared to a running counter according to a mask associated with the number of retries of the command corresponding to the entry. When the unmasked bits of the two values match, the command is retried. In one embodiment, the same portion of the buffer entry that is used to store the number of retries and the timer expiration value is alternately used to store a slave-generated tag that is received with an acknowledgment response.

    摘要翻译： 用于通过分割事务总线实现从主设备发送到从设备的命令重试的退避时序的系统和方法。 一个实施例包括具有用于存储每个未决命令和相关信息的条目的缓冲器，包括命令的重试次数和静态伪随机定时器到期值。 根据与对应于条目的命令的重试次数相关联的掩码，将每个条目的定时器到期值与运行计数器进行比较。 当两个值的未屏蔽位匹配时，将重试该命令。 在一个实施例中，用于存储重试次数和定时器到期值的缓冲器条目的相同部分交替地用于存储用确认响应接收的从生产标签。