公开(公告)号：US07326992B2

公开(公告)日：2008-02-05

申请号：US11468202

申请日：2006-08-29

Applicant: Yi Ding

Inventor： Yi Ding

IPC: H01L29/76

CPC classification number: H01L27/11526 ,  G11C16/0458 ,  H01L21/28273 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11546 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7883 ,  H01L29/7885 ,  H01L29/7887

Abstract: In a memory cell (110) having multiple floating gates (160), the select gate (140) is formed before the floating gates. In some embodiments, the memory cell also has control gates (170) formed after the select gate. Substrate isolation regions (220) are formed in a semiconductor substrate (120). The substrate isolation regions protrude above the substrate. Then select gate lines (140) are formed. Then a floating gate layer (160) is deposited. The floating gate layer is etched until the substrate isolation regions are exposed. A dielectric (164) is formed over the floating gate layer, and a control gate layer (170) is deposited. The control gate layer protrudes upward over each select gate line. These the control gates and the floating gates are defined independently of photolithographic alignment. In another aspect, a nonvolatile memory cell has at least two conductive floating gates (160). A dielectric layer (164) overlying the floating gate has a continuous feature that overlies the floating gate and also overlays a sidewall of the select gate (140). Each control gate (160) overlies the continuous feature of the dielectric layer and also overlies the floating gate. In another aspect, substrate isolation regions (220) are formed in a semiconductor substrate. Select gate lines cross over the substrate isolation regions. Each select gate line has a planar top surface, but its bottom surface goes up and down over the substrate isolation regions. Other features are also provided.

Abstract translation: 在具有多个浮动栅极（160）的存储单元（110）中，在浮置栅极之前形成选择栅极（140）。 在一些实施例中，存储器单元还具有在选择栅极之后形成的控制栅极（170）。 衬底隔离区（220）形成在半导体衬底（120）中。 衬底隔离区突出于衬底上方。 然后选择栅极线（140）。 然后沉积浮栅层（160）。 蚀刻浮栅，直到衬底隔离区露出。 在浮动栅极层上形成电介质（164），并沉积控制栅极层（170）。 控制栅极层在每个选择栅极线上向上突出。 这些控制栅极和浮置栅极独立于光刻对准来定义。 在另一方面，非易失性存储单元具有至少两个导电浮动栅极（160）。 覆盖浮动栅极的介电层（164）具有覆盖在浮动栅极上并且还覆盖选择栅极（140）的侧壁的连续特征。 每个控制栅极（160）覆盖在电介质层的连续特征上并且也覆盖在浮动栅极上。 在另一方面，衬底隔离区（220）形成在半导体衬底中。 选择栅极线跨越衬底隔离区。 每个选择栅线具有平坦的顶表面，但其底表面在衬底隔离区上方上下移动。 还提供其他功能。

公开(公告)号：US20080023748A1

公开(公告)日：2008-01-31

申请号：US11495008

申请日：2006-07-27

Applicant: Yi Ding

Inventor： Yi Ding

IPC: H01L29/788

CPC classification number: H01L27/11521 ,  H01L21/76897 ,  H01L27/115

Abstract: In some embodiments, when etching a dielectric to form a self-aligned contact opening to a source/drain region (160) of a transistor, the gate structure (220) is protected on top with a non-conformal layer (M3), possibly silicon, deposited so that it is thicker over the gate than over the source/drain region. The silicon may be insulated from the gates by another dielectric layer (M2). When the non-conformal layer is etched over the source/drain region, it may also be etched on top of the gate structure, but the gate structure remains protected due to the greater thickness of the non-conformal layer.

Abstract translation: 在一些实施例中，当蚀刻电介质以形成到晶体管的源极/漏极区域（160）的自对准接触开口时，门结构（220）在顶部受到保形层（M 3）的保护， 可能的硅沉积，使得其在栅极上比在源极​​/漏极区域上更厚。 硅可以通过另一介电层（M 2）与栅绝缘。 当非共形层在源极/漏极区域上蚀刻时，也可以在栅极结构的顶部蚀刻，但由于非共形层的厚度较大，栅极结构保持保护。

公开(公告)号：US20070262476A1

公开(公告)日：2007-11-15

申请号：US11431223

申请日：2006-05-09

Applicant: Yi Ding ,  Jason Taylor ,  Chiliang Chen

Inventor： Yi Ding ,  Jason Taylor ,  Chiliang Chen

IPC: H01L21/8238

CPC classification number: H01L21/76224 ,  H01L27/115 ,  H01L27/11521

Abstract: A process for manufacturing an integrated circuit using shallow trench isolation (STI) includes a 2-step nitride removal process which, when combined with a nitride pull-back step provides, in a floating gate memory integrated circuit, a high coupling ratio and a reduction in thinning of the tunnel oxide layer in a floating gate memory integrated circuit.

Abstract translation: 使用浅沟槽隔离（STI）制造集成电路的方法包括两步氮化物去除工艺，当与氮化物拉回步骤组合时，在浮动栅极存储器集成电路中提供高耦合比和降低 在浮动栅极存储器集成电路中的隧道氧化物层的薄化。

公开(公告)号：US20070162567A1

公开(公告)日：2007-07-12

申请号：US11332550

申请日：2006-01-12

Applicant: Yi Ding

Inventor： Yi Ding

IPC: G06F15/16

CPC classification number: H04L67/16 ,  H04L41/5045 ,  H04L67/125

Abstract: A technique is provided for dynamically extending a network device manager when a new device and/or service are added to a network. A technique for extending a rule set associated with the management system is also provided. A service discovery module discovers a new network device on a network. A service operation module (SOM) is generated for the network device. The SOM provides an interface for a management module (MM) to communicate with the network device. The SOM provides data, corresponding to the service provided by the network device, to the MM. When a client sends the MM a request for a service provided by the network device, the MM provides the service request to the SOM which forwards the request to the network device. Users of the network device manager may define rules for a network device after the network device is added to the network, wherein the MM issues a service request of a network device in response to receiving an event notification.

Abstract translation: 提供了一种技术，用于在将新设备和/或服务添加到网络时动态地扩展网络设备管理器。 还提供了用于扩展与管理系统相关联的规则集的技术。 服务发现模块在网络上发现新的网络设备。 为网络设备生成服务操作模块（SOM）。 SOM提供用于管理模块（MM）与网络设备进行通信的接口。 SOM向MM提供与网络设备提供的服务相对应的数据。 当客户端向MM发送由网络设备提供的服务的请求时，MM向SOM提供服务请求，SOM将请求转发给网络设备。 在网络设备被添加到网络之后，网络设备管理器的用户可以定义网络设备的规则，其中MM响应于接收到事件通知而发布网络设备的服务请求。

公开(公告)号：US07238983B2

公开(公告)日：2007-07-03

申请号：US11321982

申请日：2005-12-28

Applicant: Yi Ding

Inventor： Yi Ding

IPC: H01L29/788

CPC classification number: H01L29/66825 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/7881

Abstract: In a nonvolatile memory, the select gates (144S) are formed from one conductive layer (e.g. polysilicon or polyside), and the wordlines (144) interconnecting the select gates are made from a different conductive layer (e.g. metal). The wordlines overlie an interlevel dielectric (310) formed over control gates (134). The dielectric thickness can be controlled to reduce the capacitance between the wordlines and the control gates. In some embodiments, the floating gates (120) are fabricated in a self-aligned manner using an isotropic etch of the floating gate layer.

公开(公告)号：US07238575B2

公开(公告)日：2007-07-03

申请号：US10798475

申请日：2004-03-10

Applicant: Yi Ding

Inventor： Yi Ding

IPC: H01L21/8239

CPC classification number: H01L29/66825 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/7881

Abstract: In a nonvolatile memory, the select gates (144S) are formed from one conductive layer (e.g. polysilicon or polyside), and the wordlines (144) interconnecting the select gates are made from a different conductive layer (e.g. metal). The wordlines overlie an interlevel dielectric (310) formed over control gates (134). The dielectric thickness can be controlled to reduce the capacitance between the wordlines and the control gates. In some embodiments, the floating gates (120) are fabricated in a self-aligned manner using an isotropic etch of the floating gate layer.

Abstract translation: 在非易失性存储器中，选择栅极（144S）由一个导电层（例如多晶硅或多边形）形成，并且互连选择栅极的字线（144）由不同的导电层（例如金属）制成。 字线覆盖在控制栅极（134）上形成的层间电介质（310）。 可以控制电介质厚度以减小字线和控制门之间的电容。 在一些实施例中，使用浮动栅极层的各向同性蚀刻，以自对准的方式制造浮置栅极（120）。

公开(公告)号：US07215841B2

公开(公告)日：2007-05-08

申请号：US11019718

申请日：2004-12-21

Applicant: Everett X. Wang ,  Sai Yu ,  Yi Ding ,  Dmitri E. Nikonov

Inventor： Everett X. Wang ,  Sai Yu ,  Yi Ding ,  Dmitri E. Nikonov

IPC: G02B6/26

CPC classification number: G02B6/12007 ,  G02B6/13

Abstract: Provided are a method and a system, wherein optical beams of a plurality of wavelengths are directed through a plurality of optical devices, wherein waveguides comprising the optical devices have different fabrication errors, and wherein the waveguides have a plurality of waveguide lengths and a plurality of waveguide widths. Optical phase errors corresponding to the waveguides are measured by the optical devices. A determination is made of the components of the optical phase errors for the waveguides from the measured phase errors.

Abstract translation: 提供了一种方法和系统，其中多个波长的光束被引导通过多个光学器件，其中包括光学器件的波导具有不同的制造误差，并且其中波导具有多个波导长度和多个 波导宽度。 通过光学器件测量与波导对应的光学相位误差。 根据测量的相位误差确定波导的光学相位误差的分量。

公开(公告)号：US20060128097A1

公开(公告)日：2006-06-15

申请号：US11348993

申请日：2006-02-07

Applicant: Yi Ding

Inventor： Yi Ding

IPC: H01L21/336

CPC classification number: H01L27/11526 ,  G11C16/0458 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11546

Abstract: In a nonvolatile memory cell (110), the select gate transistor is formed as a buried channel transistor to increase the transistor current.

公开(公告)号：US07052947B2

公开(公告)日：2006-05-30

申请号：US10632154

申请日：2003-07-30

Applicant: Yi Ding

Inventor： Yi Ding

IPC: H01L21/8238

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11546

Abstract: In fabrication of a nonvolatile memory cell having two floating gates, one or more peripheral transistor gates are formed from the same layer (140) as the select gate. The gate dielectric (130) for these peripheral transistors and the gate dielectric (130) for the select gates are formed simultaneously. In a nonvolatile memory having a memory cell with two floating gates, the gate dielectric (130) for the peripheral transistors and the gate dielectric (130) for the select gates (140) have the same thickness.

Abstract translation: 在具有两个浮置栅极的非易失性存储单元的制造中，与选择栅极相同的层（140）形成一个或多个外围晶体管栅极。 用于这些外围晶体管的栅极电介质（130）和用于选择栅极的栅极电介质（130）同时形成。 在具有具有两个浮置栅极的存储单元的非易失性存储器中，用于外围晶体管的栅极电介质（130）和选择栅极（140）的栅极电介质（130）具有相同的厚度。

公开(公告)号：US20050287741A1

公开(公告)日：2005-12-29

申请号：US10879782

申请日：2004-06-28

Applicant: Yi Ding

Inventor： Yi Ding

IPC: H01L21/336 ,  H01L21/8236 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/115

CPC classification number: H01L27/11531 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526

Abstract: A first dielectric (120) and a first floating gate layer (130.1) are formed on a semiconductor substrate (110). The first dielectric, the first floating gate layer, and the substrate are etched to form isolation trenches (150). The first dielectric (120) is etched to pull the first dielectric away from the trench edges (150E) and/or the edges of the first floating gate layer (130E). The trench edges and/or the edges of the first floating gate layer are then oxidized. The trenches are filled with a second dielectric (210.2), which is then etched laterally adjacent to the edges of the trench and the first floating gate layer. A second floating gate layer (130.2) is formed to extend into the regions which were occupied by the second dielectric before it was etched.

Abstract translation: 第一电介质（120）和第一浮栅（130.1）形成在半导体衬底（110）上。 蚀刻第一电介质，第一浮栅层和衬底以形成隔离沟槽（150）。 蚀刻第一电介质（120）以将第一电介质拉离第一浮动栅层（​​130E）的沟槽边缘（150E）和/或边缘。 然后，第一浮栅层的沟槽边缘和/或边缘被氧化。 沟槽填充有第二电介质（210.2），然后将其邻近蚀刻到沟槽和第一浮栅层的边缘。 第二浮栅层（130.2）被形成为延伸到被蚀刻之前由第二电介质占据的区域。