公开(公告)号：US20040211990A1

公开(公告)日：2004-10-28

申请号：US10470594

申请日：2003-10-14

申请人： Sanyo Electric Co., Ltd.

发明人： Tetsuro Asano ,  Mikito Sakakibara ,  Yoshibumi Nakajima ,  Hidetoshi Ishihara

IPC分类号： H01L029/80

CPC分类号： H01L21/761 ,  H01L21/76283 ,  H01L21/823481 ,  H01L27/0605 ,  H01L27/0629 ,  H01L29/42316 ,  H01L29/812

摘要： A semiconductor switching device includes a plurality of metal layers. At least one of the metal layers forming a Schottky junction with a semi-insulating substrate or an insulating layer on a substrate. The device also includes an impurity diffusion region, and a high-concentration impurity region formed between two of the metal layers or between one of the metal layers and the impurity diffusion region so as to suppress expansion of a depletion layer from the corresponding metal layer.

摘要翻译： 半导体开关器件包括多个金属层。 至少一个金属层与半绝缘基板或基板上的绝缘层形成肖特基结。 该器件还包括杂质扩散区域和形成在两个金属层之间或金属层之间的金属层和杂质扩散区域之间的高浓度杂质区域，以便抑制耗尽层从相应金属层的膨胀。

公开(公告)号：US20040203196A1

公开(公告)日：2004-10-14

申请号：US10452284

申请日：2003-06-03

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Tsuneaki Fuse

IPC分类号： H01L021/8238 ,  H01L029/80 ,  H01L031/112

CPC分类号： H01L27/1203 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/11807

摘要： A semiconductor integrated circuit of an aspect of the present invention having a CMOS logic gate including a first MOS transistor of a first conductivity type and a second MOS transistor of a second conductivity type, has a first MOS transistor region in which the first MOS transistor is formed, and a 2ath MOS transistor region and a 2bth MOS transistor region, in each of which the second MOS transistor is formed, separately arranged to be in contact with a first side of said first MOS transistor region and a second side opposite to the first side.

摘要翻译： 具有包括第一导电类型的第一MOS晶体管和第二导电类型的第二MOS晶体管的CMOS逻辑门的本发明的半导体集成电路具有第一MOS晶体管区域，其中第一MOS晶体管是 以及分别设置成与所述第一MOS晶体管区域的第一侧接触的第二MOS晶体管区域和形成有第二MOS晶体管的第二MOS晶体管区域和第二第二MOS晶体管区域的第二MOS晶体管区域和第二MOS晶体管区域， 侧。

公开(公告)号：US20040178443A1

公开(公告)日：2004-09-16

申请号：US10384144

申请日：2003-03-10

申请人： Semiconductor Components Industries, LLC.

发明人： Zia Hossain ,  Mohamed Imam ,  Joe Fulton

IPC分类号： H01L029/80 ,  H01L031/112 ,  H01L029/76 ,  H01L029/94

CPC分类号： H01L29/7835 ,  H01L29/0615 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0878

摘要： A structure for making a LDMOS transistor (100) includes an interdigitated source finger (26) and a drain finger (21) on a substrate (15). Termination regions (35, 37) are formed at the tips of the source finger and drain finger. A drain (45) of a second conductivity type is formed in the substrate of a first conductivity type. A field reduction region (7) of a second conductivity type is formed in the drain and is wrapped around the termination regions for controlling the depletion at the tip and providing higher voltage breakdown of the transistor.

摘要翻译： 用于制造LDMOS晶体管（100）的结构在衬底（15）上包括交叉指状的源极指（26）和漏极指（21）。 终端区域（35,37）形成在源极指和漏极指的尖端处。 在第一导电类型的衬底中形成第二导电类型的漏极（45）。 在漏极中形成第二导电类型的场致还区域（7），并且围绕终端区域缠绕以控制尖端的耗尽并提供晶体管的较高的电压击穿。

公开(公告)号：US20040135178A1

公开(公告)日：2004-07-15

申请号：US10681126

申请日：2003-10-09

发明人： Hidekatsu Onose ,  Hideo Homma ,  Atsuo Watanabe

IPC分类号： H01L029/80 ,  H01L031/112

CPC分类号： H01L29/1066 ,  H01L29/1608 ,  H01L29/7722

摘要： A semiconductor device includes a trench formed on the source side of the drift region, the p-type gate region and the gate formed at the bottom of the trench, and the source formed over the entire surface of the unit device through the insulating film. The narrowest portion of the channel is deeper than one-half the junction depth of the p-type gate region. This allows the width of the channel on the drain side to be reduced even with a lower energy.

摘要翻译： 半导体器件包括在漂移区的源极侧形成的沟槽，形成在沟槽底部的p型栅极区域和栅极，并且源极通过绝缘膜形成在单元器件的整个表面上。 通道的最窄部分比p型栅极区域的结深的一半更深。 这允许即使在较低的能量下也可以减小漏极侧的通道的宽度。

公开(公告)号：US20040124444A1

公开(公告)日：2004-07-01

申请号：US10442492

申请日：2003-05-21

发明人： Amol M. Kalburge ,  Kevin Q. Yin

IPC分类号： H01L029/80

CPC分类号： H01L29/66272 ,  H01L29/0804 ,  H01L29/66242 ,  H01L29/66287

摘要： According to one exemplary embodiment, a bipolar transistor comprises a base having a top surface. The bipolar transistor further comprises a first link spacer and a second link spacer situated on the top surface of the base. The bipolar transistor further comprises a sacrificial post situated between the first and second link spacers, where the first and second link spacers have a height that is substantially less than a height of the sacrificial post. The bipolar transistor also comprises a conformal layer situated over the sacrificial post and the first and second link spacers. According to this exemplary embodiment, the bipolar transistor further comprises a sacrificial planarizing layer situated over the conformal layer, the first and second link spacers, the sacrificial post, and the base. The sacrificial planarizing layer may comprise, for example, an organic material such as an organic BARC (nullbottom anti-reflective coatingnull).

摘要翻译： 根据一个示例性实施例，双极晶体管包括具有顶表面的基座。 双极晶体管还包括第一连接间隔物和位于基底的顶表面上的第二连接间隔物。 所述双极晶体管还包括位于所述第一和第二连接间隔件之间的牺牲柱，其中所述第一和第二连接间隔件的高度实质上小于所述牺牲柱的高度。 双极晶体管还包括位于牺牲柱和第一和第二连接间隔物之上的共形层。 根据该示例性实施例，双极晶体管还包括位于保形层之上的牺牲平坦化层，第一和第二连接间隔物，牺牲柱和基底。 牺牲平坦化层可以包括例如有机材料，例如有机BARC（“底部抗反射涂层”）。

公开(公告)号：US20040117054A1

公开(公告)日：2004-06-17

申请号：US10318967

申请日：2002-12-13

申请人： LAM RESEARCH CORPORATION

发明人： Yehiel Gotkis ,  Vladimir Katz ,  David Hemker ,  Rodney Kistler ,  Nicolas J. Bright

IPC分类号： H01L031/112 ,  H01L031/0288 ,  H01L029/80 ,  G06F019/00 ,  G05B013/02

CPC分类号： G05B23/0254 ,  H01L22/26

摘要： A method for converting a slope based detection task to a threshold based detection task is provided. The method initiates with defining an approximation equation for a set of points corresponding to values of a process being monitored. Then, an expected value at a current point of the process being monitored is predicted. Next, a difference between a measured value at the current point of the process being monitored and the corresponding expected value is calculated. Then, the difference is monitored for successive points to detect a deviation value between the measured value and the expected value. Next, a transition point for the process being monitored is identified based on the detection of the deviation value. A processing system configured to provide real time data for a slope based transition and a computer readable media are also provided.

摘要翻译： 提供了一种将基于斜率的检测任务转换为基于阈值的检测任务的方法。 该方法通过为对应于被监视的进程的值的一组点定义近似方程来启动。 然后，预测在被监视的处理的当前点的期望值。 接下来，计算被监视处理当前点的测量值与对应的期望值之间的差值。 然后，对连续点监测差异，以检测测量值和预期值之间的偏差值。 接下来，基于偏差值的检测来识别被监视处理的转变点。 还提供了一种处理系统，其被配置为提供用于基于斜率的转换的实时数据和计算机可读介质。

公开(公告)号：US20040089886A1

公开(公告)日：2004-05-13

申请号：US10696040

申请日：2003-10-30

发明人： Hidetaka Hattori ,  Masakazu Yamaguchi

IPC分类号： H01L029/80

CPC分类号： H01L29/7813 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/6634 ,  H01L29/66348 ,  H01L29/7393 ,  H01L29/7395 ,  H01L29/7396 ,  H01L29/7397 ,  H01L29/7455

摘要： In a p-type base layer of a trench IGBT comprising a p-type collector layer, an n-type base layer formed on the p-type collector layer, the p-type base layer formed on the n-type base layer, and an n-type emitter layer formed on the surface of the p-type base layer, the point of the highest impurity concentration is located closer to the n-type base layer than the junction with the emitter layer. In other words, the pinch-off of the channel is generated in the position closer to the n-type base layer than to the junction between the p-type base layer and the n-type emitter layer.

摘要翻译： 在包括p型集电极层的p型基极层，形成在p型集电极层上的n型基极层，形成在n型基极层上的p型基极层，以及 形成在p型基底层的表面上的n型发射极层，杂质浓度最高的点比与发射极层的结更靠近n型基极层。 换句话说，在比p型基极层和n型发射极层之间的结点更靠近n型基极层的位置产生沟道的夹断。

公开(公告)号：US20040089884A1

公开(公告)日：2004-05-13

申请号：US10703582

申请日：2003-11-10

发明人： Kyo Seop Choo ,  June Ho Park

IPC分类号： H01L029/80

CPC分类号： H01L27/14692 ,  H01L27/124 ,  H01L27/14601 ,  H01L27/14676 ,  H01L31/0272

摘要： A TFT array panel and a method for fabricating the same is disclosed, wherein an adhesion force between an elongated wire and a TFT array panel pad is improved by increasing the contact area of a bonding pad. The TFT array panel pad includes a first conductive layer formed in a pad region on an insulating substrate. The first conductive layer includes a plurality of conductive islands and holes. A second conductive layer is formed over and covers the first conductive layer.

摘要翻译： 公开了一种TFT阵列面板及其制造方法，其中通过增加接合焊盘的接触面积来提高细长线和TFT阵列面板衬垫之间的粘附力。 TFT阵列面板焊盘包括形成在绝缘基板上的焊盘区域中的第一导电层。 第一导电层包括多个导电岛和孔。 在第一导电层上形成第二导电层并覆盖第一导电层。

公开(公告)号：US20040046188A1

公开(公告)日：2004-03-11

申请号：US10637693

申请日：2003-08-11

申请人： Hitachi, Ltd

发明人： Kiyoo Itoh ,  Koichiro Ishibashi

IPC分类号： H01L029/80

CPC分类号： H01L27/105 ,  G11C11/412 ,  G11C11/413 ,  G11C11/417 ,  H01L27/1104 ,  H01L27/1116 ,  Y10S257/903

摘要： A static memory cell, composed of cross-coupled MOS transistors having a relatively high threshold voltage, is equipped with MOS transistors for controlling the power supply line voltage of the memory cell. To permit the voltage difference between two data storage nodes in the inactivated memory cell to exceed the voltage difference between the two nodes when write data is applied from a data line pair DL and /DL to the two nodes in the activated memory cell, the power supply line voltage control transistors are turned on to apply a high voltage VCH to the power supply lines after the word line voltage is turned off. The data holding voltage in the memory cell can be activated to a high voltage independent of the data line voltage, and the data holding voltage can be dynamically set so that read and write operations can be performed at high speed with low power consumption.

摘要翻译： 由具有相对高阈值电压的交叉耦合MOS晶体管组成的静态存储单元配备有用于控制存储单元的电源线电压的MOS晶体管。 为了在从数据线对DL和/ DL向激活的存储单元中的两个节点施加写入数据时，允许非激活存储单元中的两个数据存储节点之间的电压差超过两个节点之间的电压差， 电源线电压控制晶体管导通，在字线电压关闭后，向电源线施加高电压VCH。 存储单元中的数据保持电压可以独立于数据线电压而被激活到高电压，并且可以动态地设置数据保持电压，使得能够以低功耗高速执行读和写操作。

公开(公告)号：US20040026722A1

公开(公告)日：2004-02-12

申请号：US10294880

申请日：2002-11-14

发明人： Ichiro Fujimori

IPC分类号： H01L029/80

CPC分类号： H01L27/0928 ,  H01L21/761 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/092 ,  Y10S438/914

摘要： A system and method for reducing noise in a substrate of a chip is provided. The system may include a substrate (70) doped with a first dopant. A first well (80) may be disposed on the substrate and doped with a second dopant. A second well (120) may be disposed within the first well (80) and doped with the second kind of dopant. A first transistor (100) may include one or more first transistor components disposed in the second well (120). The first transistor (100) may be adapted to employ a first type of channel having a quiet voltage source (140) connected to a body thereof. A third well (110) may be disposed within the first well (80) and doped with the first kind of dopant. A second transistor (90) may include one or more second transistor components that may be disposed in the third well (110). The second transistor (90)may be adapted to employ a second type of channel. The first well (80) may shield the substrate (70) from noise in the second well (120) and third well (110).

摘要翻译： 提供了一种用于降低芯片的衬底中的噪声的系统和方法。 该系统可以包括掺杂有第一掺杂剂的衬底（70）。 第一阱（80）可以设置在衬底上并掺杂有第二掺杂剂。 第二阱（120）可以设置在第一阱（80）内并掺杂第二种掺杂剂。 第一晶体管（100）可以包括设置在第二阱（120）中的一个或多个第一晶体管组件。 第一晶体管（100）可以适于采用具有连接到其主体的安静电压源（140）的第一类型的沟道。 第三阱（110）可以设置在第一阱（80）内并掺杂第一种掺杂剂。 第二晶体管（90）可以包括可设置在第三阱（110）中的一个或多个第二晶体管组件。 第二晶体管（90）可以适于采用第二类型的通道。 第一阱（80）可以屏蔽衬底（70）免受第二阱（120）和第三阱（110）中的噪声。