公开(公告)号：US20040256678A1

公开(公告)日：2004-12-23

申请号：US10816188

申请日：2004-04-02

申请人： Sanyo Electric Co., Ltd.

发明人： Kazutomo Goshima ,  Toshiyuki Ohkoda ,  Toshimitsu Taniguchi

IPC分类号： H01L029/80

CPC分类号： H01L21/8249 ,  H01L27/0623 ,  H01L29/7322 ,  H01L29/735

摘要： The invention is directed to reducing of the number of steps in a BiCMOS process. A first N-well 3A and a second N-well 3B are formed deeply on a surface of a P-type semiconductor substrate. A first P-well 4A is formed in the first N-well 3A, and an N-channel MOS transistor is formed in the first P-well 4A. The second N-well 3B is used as a collector of a vertical NPN bipolar transistor. A second P-well 4B is formed in the second N-well 3B. The second P-well 4B is formed simultaneously with the first P-well 4A. The second P-well 4B is used as a base of the vertical NPN bipolar transistor. An Nnull emitter layer and a Pnull base electrode layer of the vertical NPN bipolar transistor are formed on a surface of the second P-well 4B.

摘要翻译： 本发明旨在减少BiCMOS工艺中的步骤数量。 第一N阱3A和第二N阱3B深深地形成在P型半导体衬底的表面上。 第一P阱4A形成在第一N阱3A中，并且在第一P阱4A中形成N沟道MOS晶体管。 第二N阱3B用作垂直NPN双极晶体管的集电极。 在第二N阱3B中形成第二P阱4B。 第二P阱4B与第一P阱4A同时形成。 第二P阱4B用作垂直NPN双极晶体管的基极。 在第二P阱4B的表面上形成垂直NPN双极晶体管的N +发射极层和P +基极电极层。

公开(公告)号：US20040232456A1

公开(公告)日：2004-11-25

申请号：US10443891

申请日：2003-05-23

发明人： Sungkwon Hong

IPC分类号： H01L029/80

CPC分类号： H01L27/1462 ,  H01L27/14609 ,  H01L27/14636 ,  H01L27/14689

摘要： The invention provides an elevated photodiode for image sensors and methods of formation of the photodiode. Elevated photodiodes permit a decrease in size requirements for pixel sensor cells while reducing leakage, image lag and barrier problems typically associated with conventional photodiodes.

摘要翻译： 本发明提供了用于图像传感器的升高的光电二极管和形成光电二极管的方法。 升高的光电二极管可以减小像素传感器单元的尺寸要求，同时减少通常与常规光电二极管相关的泄漏，图像滞后和屏障问题。

公开(公告)号：US20040207454A1

公开(公告)日：2004-10-21

申请号：US10819976

申请日：2004-04-08

申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

发明人： Kenichi Hidaka ,  Katsushi Tara ,  Tadayoshi Nakatsuka

IPC分类号： H01L029/80

CPC分类号： H03K17/687 ,  H03J2200/29

摘要： One end of each of five resistors is connected to each of the two ends and the respective intermediate points of a cascade of four depression-type FETs, while the other ends of the five resistors are provided with a predetermined voltage. This configuration fixes the source-drain potential of the four FETs. This fixing of the source-drain potential of the FETs permits stable application of a bias voltage for turning ON the FETs between the gate and the source each FET, so as to ensure the ON-OFF switching of the FETs.

摘要翻译： 五个电阻器中的每一个的一端连接到四个凹陷型FET的级联的两端和各中间点中的每一个，而五个电阻器的另一端设置有预定电压。 该配置修复了四个FET的源极 - 漏极电位。 FET的源极 - 漏极电位的这种固定允许稳定地施加用于导通栅极和源极FET之间的FET的偏置电压，以确保FET的导通切换。

公开(公告)号：US20040195695A1

公开(公告)日：2004-10-07

申请号：US10827064

申请日：2004-04-19

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Cyril Cabral, JR. ,  Roy Arthur Carruthers ,  James McKell Edwin Harper ,  Christian Lavoie ,  Ronnen Andrew Roy ,  Yun Yu Wang

IPC分类号： H01L029/80 ,  H01L021/44

CPC分类号： H01L21/28518

摘要： A method of reducing the contact resistance of metal suicides to the pnull silicon area or the nnull silicon area of the substrate comprising: (a) forming a metal germanium (Ge) layer over a silicon-containing substrate, wherein said metal is selected from the group consisting of Co, Ti, Ni and mixtures thereof; (b) optionally forming an oxygen barrier layer over said metal germanium layer; (c) annealing said metal germanium layer at a temperature which is effective in converting at least a portion thereof into a substantially non-etchable metal silicide layer, while forming a SinullGe interlayer between said silicon-containing substrate and said substantially non-etchable metal silicide layer; and (d) removing said optional oxygen barrier layer and any remaining alloy layer. When a Co or Ti alloy is employed, e.g., ConullGe or TinullGe, two annealing steps are required to provide the lowest resistance phase of those metals, whereas, when Ni is employed, a single annealing step forms the lowest resistance phase of Ni silicide.

摘要翻译： 一种降低金属硅化物与衬底的p +硅区域或n +硅区域的接触电阻的方法，包括：（a）在含硅衬底上形成金属锗（Ge）层，其中所述金属选自 由Co，Ti，Ni及其混合物组成的组; （b）任选地在所述金属锗层上形成氧阻隔层; （c）在有效地将其至少一部分转化成基本上不可蚀刻的金属硅化物层的温度下退火所述金属锗层，同时在所述含硅衬底和所述基本上不可蚀刻的衬底之间形成Si-Ge中间层 金属硅化物层; 和（d）去除所述任选的氧气阻挡层和任何剩余的合金层。 当使用Co或Ti合金时，例如Co-Ge或Ti-Ge，需要两个退火步骤来提供这些金属的最低电阻相，而在使用Ni时，单个退火步骤形成最低的电阻相 的Ni硅化物。

公开(公告)号：US20040051124A1

公开(公告)日：2004-03-18

申请号：US10657236

申请日：2003-09-09

申请人： NEC ELECTRONICS CORPORATION

发明人： Toru Kawasaki

IPC分类号： H01L029/80 ,  H01L031/112

CPC分类号： H01L27/14643 ,  H01L27/14623 ,  H01L27/1463

摘要： Shift register electrodes are formed in an imaging area and a peripheral area through use of a single layer of conductive film, and a thick insulating film is deposited over those electrodes and planarized. The thick insulating film overlying the shift register electrodes in the peripheral area is kept as it is and on the other hand, the thick insulating film overlying the shift register electrodes is etched to just fill gaps between the shift register electrodes with the film, thereby allowing a light shielding metal layer overlying the shift register electrodes in the peripheral area and insulating films sandwiched therebetween to be formed without discontinuity. Since metal interconnect lines in the peripheral area have a thick and planarized insulating film formed thereunder, parasitic capacitance between diffusion layers/electrodes and the metal interconnect lines can be reduced, leading to reduction in power consumption of image sensor.

摘要翻译： 移位寄存器电极通过使用单层导电膜形成在成像区域和外围区域中，并且在这些电极上沉积厚的绝缘膜并进行平坦化。 覆盖周边区域中的移位寄存器电极的厚绝缘膜保持原样，另一方面，覆盖移位寄存器电极的厚绝缘膜被蚀刻以仅填充移位寄存器电极与膜之间的间隙，从而允许 覆盖周边区域中的移位寄存器电极的遮光金属层和夹在其间的绝缘膜，而不间断地形成。 由于周边区域的金属布线具有在其上形成的厚且平坦化的绝缘膜，所以可以减小扩散层/电极和金属互连线之间的寄生电容，从而降低图像传感器的功耗。

公开(公告)号：US20040007723A1

公开(公告)日：2004-01-15

申请号：US10193783

申请日：2002-07-11

申请人： International Rectifier Corp.

发明人： Kohji Andoh ,  Davide Chiola

IPC分类号： H01L029/80 ,  H01L027/095 ,  H01L029/47

CPC分类号： H01L29/407 ,  H01L27/0814 ,  H01L29/66143 ,  H01L29/8725 ,  Y10S438/963

摘要： A fabrication process for a Schottky barrier structure includes forming a nitride layer directly on a surface of an epitaxial (nullepinull) layer and subsequently forming a plurality of trenches in the epi layer. The interior walls of the trenches are then deposited with a final oxide layer without forming a sacrificial oxide layer to avoid formation of a beak bird at the tops of the interior trench walls. A termination trench is etched in the same process step for forming the plurality of trenches in the active area.

摘要翻译： 用于肖特基势垒结构的制造方法包括在外延（“epi”）层的表面上直接形成氮化物层，随后在外延层中形成多个沟槽。 然后将沟槽的内壁沉积有最终的氧化物层，而不形成牺牲氧化物层，以避免在内部沟槽壁的顶部形成喙鸟。 在用于在有源区域中形成多个沟槽的相同工艺步骤中蚀刻端接沟槽。

公开(公告)号：US20030227320A1

公开(公告)日：2003-12-11

申请号：US10163786

申请日：2002-06-05

申请人： Intel Corporation

发明人： Jeffrey B. Davis

IPC分类号： H01L029/80

CPC分类号： H03K19/00384 ,  H01L27/0705 ,  H01L27/098 ,  H03K17/567

摘要： An integrated circuit includes an output buffer operable to drive an output node. The output buffer may comprise a MOSFET having a JFET integrated within a portion of a drain region of the MOSFET. The JFET may comprise a gate of second conductivity formed in semiconductor material of first conductivity type, which is contiguous with the drain region for the MOSFET. A voltage shaping circuit may control a bias of the JFET gate in accordance with the voltage levels of an output node and a predetermined output impedance.

公开(公告)号：US20030178654A1

公开(公告)日：2003-09-25

申请号：US10391402

申请日：2003-03-17

发明人： Trevor J. Thornton

IPC分类号： H01L029/80

CPC分类号： H01L27/095 ,  H01L29/739 ,  H01L29/7606 ,  H01L29/812

摘要： Various methods for forming semiconductor devices are provided that include the step of implanting dopants into the devices to achieve doping concentrations that allow complementary n- and p-channel SJT behavior with devices of substantially equal gate length and gate width. Moreover, complementary SJT devices are provided that include n- and p-channel devices that have approximately equal gate lengths and widths. SJT devices may be appropriately doped and configured such that input current and the output current both vary substantially exponentially with a gate-source voltage in the sub-threshold mode, and such that the drain current varies substantially linearly with the gate current through a substantially constant current gain that is given by a ratio of the drain current to the gate current.

摘要翻译： 提供了用于形成半导体器件的各种方法，其包括将掺杂剂注入到器件中以实现掺杂浓度以允许具有基本相等的栅极长度和栅极宽度的器件的互补n沟道和p沟道SJT行为的步骤。 此外，提供了互补的SJT器件，其包括具有大致相等的栅极长度和宽度的n沟道和p沟道器件。 SJT器件可以被适当地掺杂和配置，使得输入电流和输出电流都以亚阈值模式中的栅极 - 源极电压大致指数地变化，并且使得漏极电流随着栅极电流基本上恒定地大致线性变化 电流增益由漏极电流与栅极电流的比值给出。

公开(公告)号：US20030107061A1

公开(公告)日：2003-06-12

申请号：US10164427

申请日：2002-06-10

申请人： Mitsubishi Denki Kabushiki Kaisha

发明人： Hiroki Ootera

IPC分类号： H01L029/80

CPC分类号： H01L21/76224 ,  H01L21/762

摘要： Noise-reduced semiconductor devices operating at a high frequency band greater than several GHz are disclosed. Also disclosed is a method for manufacturing such semiconductor devices. A trench penetrating through a semiconductor substrate is configured to surround a noise-generating circuit block and/or a noise-susceptible circuit block, in order to reduce noise propagation through the substrate. Noise-reduced semiconductor device are fabricated with a conventional silicon wafer instead of an SOI (Silicon on Insulator) wafer, which is manufactured in a complicated process sequence.

摘要翻译： 公开了在大于几GHz的高频带工作的降噪半导体器件。 还公开了一种用于制造这种半导体器件的方法。 穿过半导体衬底的沟槽被配置为围绕噪声产生电路块和/或噪声敏感电路块，以便减少通过衬底的噪声传播。 使用传统的硅晶片代替以复杂工艺顺序制造的SOI（绝缘体上硅）晶片制造降噪半导体器件。

公开(公告)号：US20030107060A1

公开(公告)日：2003-06-12

申请号：US10313037

申请日：2002-12-06

申请人： Taiyo Yuden Co., Ltd.

发明人： Kenichi Ota ,  Manabu Satomi ,  Masayuki Fujimoto

IPC分类号： H01L029/80

CPC分类号： H01L23/645 ,  H01L21/8252 ,  H01L23/50 ,  H01L23/5389 ,  H01L23/642 ,  H01L24/48 ,  H01L27/0605 ,  H01L27/0688 ,  H01L28/10 ,  H01L28/40 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/85424 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

摘要： A composite module and its production process which allow multiple functions, miniaturization, low power consumption and low costs without requiring any external chip parts at all. A high-frequency integrated circuit is embedded in a silicon substrate, a high-frequency high-capacity bypass capacitor and a matching coil using thin films of different types of materials are also formed on the silicon substrate, a high-frequency high-capacity bypass capacitor is further formed with an interlayer insulation film between them, and these elements and the high-frequency integrated circuit are connected via a wiring layer.

摘要翻译： 复合模块及其生产过程，可以实现多种功能，小型化，低功耗和低成本，而无需任何外部芯片部件。 高频集成电路嵌入硅衬底中，高频大容量旁路电容器和使用不同类型材料的薄膜的匹配线圈也形成在硅衬底上，高频高容量旁路 电容器还在其间形成有层间绝缘膜，并且这些元件和高频集成电路经由布线层连接。