公开(公告)号：US5561690A

公开(公告)日：1996-10-01

申请号：US346067

申请日：1994-11-29

申请人： Yong-Gyu Park

发明人： Yong-Gyu Park

IPC分类号： H03M7/40 ,  H03M7/42 ,  H03D1/00

CPC分类号： H03M7/425

摘要： A variable length code (VLC) decoding apparatus for decoding sequential variable length codewords includes a second barrel shifter cascaded to a first barrel shifter for providing a second table memory device with a decoding window output sequence which is directly shifted in response to a codeword length output from a first table memory device so that the first bit in the decoding window output sequence is the first bit of the next variable length codeword in a decoding window output sequence from the first barrel shifter; and the second table memory device for producing a fixed length codeword in response to each variable length codeword in the second decoding window output sequence, to thereby decode, at each clock cycle, consecutively two variable length codewords without an operational delay in an accumulator for shifting the decoding window of the first barrel shifter.

摘要翻译： 用于解码顺序可变长度码字的可变长度码（VLC）解码装置包括级联到第一桶形移位器的第二桶形移位器，用于向第二表存储器装置提供响应于码字长度输出直接移位的解码窗口输出序列 使得解码窗口输出序列中的第一位是来自第一桶形移位器的解码窗口输出序列中的下一个可变长度码字的第一位; 以及第二表存储器装置，用于响应于第二解码窗输出序列中的每个可变长度码字产生固定长度码字，从而在每个时钟周期连续解码两个可变长度码字，而不存在用于移位的累加器中的操作延迟 第一桶形移位器的解码窗口。

公开(公告)号：US5561422A

公开(公告)日：1996-10-01

申请号：US242914

申请日：1994-05-16

申请人： Kyung-Jin Kim

发明人： Kyung-Jin Kim

IPC分类号： H03M7/42 ,  H03M7/40

CPC分类号： H03M7/42

摘要： An encoding apparatus having a 16-bit read-only-memory(ROM) and a general 16-bit microprocessor comprises: means for storing variable length code table data which is originally of 18 bit length in said ROM, means for processing a source code inputted from an input line in said microprocessor to convert said source code into an appropriate form for accessing said variable length code table data stored in said ROM so as to determine the length of the variable length code, and means for transmitting said variable length code of said determined length through a transmission line.

摘要翻译： 一种具有16位只读存储器（ROM）和一般16位微处理器的编码装置包括：用于存储在ROM中最初具有18位长度的可变长度码表数据的装置，用于处理源代码 从所述微处理器的输入线输入，将所述源代码转换成适当的形式，用于访问存储在所述RO​​M中的所述可变长度码表数据，以便确定可变长度码的长度;以及用于发送所述可变长度码的装置 所述确定的长度通过传输线。

公开(公告)号：US5550542A

公开(公告)日：1996-08-27

申请号：US238362

申请日：1994-05-04

申请人： Shuji Inoue

发明人： Shuji Inoue

IPC分类号： H04N7/26 ,  H03M7/42 ,  H04N1/41 ,  H03M7/40

CPC分类号： H03M7/425

摘要： A variable length decoder for decoding a variable length code. The variable length decoder includes a code length look-up table which receives n-j bits of an n-bit fixed-length word. A segment of the variable length code value is held in the n-j bits where n and j are integers and j is less than or equal to n. The code length look-up table produces a decoded code length value. The variable length decoder includes a code value look-up table which receives the n-bit fixed-length word and produces a decoded code value of the variable length code.

摘要翻译： 一种用于解码可变长度码的可变长度解码器。 可变长度解码器包括接收n位固定长度字的n-j个比特的码长查找表。 可变长度代码值的段被保存在n-j位中，其中n和j是整数，并且j小于或等于n。 码长查找表产生解码码长度值。 可变长度解码器包括接收n位固定长度字并产生可变长度码的解码码值的码值查找表。

公开(公告)号：US5539401A

公开(公告)日：1996-07-23

申请号：US483035

申请日：1995-06-07

申请人： Satoshi Kumaki ,  Kazuya Ishihara ,  Shinichi Nakagawa ,  Atsuo Hanami

发明人： Satoshi Kumaki ,  Kazuya Ishihara ,  Shinichi Nakagawa ,  Atsuo Hanami

IPC分类号： H04N19/60 ,  G06T9/00 ,  H03M7/42 ,  H04N1/41 ,  H04N1/411 ,  H04N19/423 ,  H04N19/426 ,  H04N19/625 ,  H04N19/93 ,  H03M7/40

CPC分类号： H03M7/42 ,  G06T9/005 ,  H04N1/411

摘要： A variable-length code table, which is used for producing a variable-length code from data formed of one set of first and second equal-length components, stores at an address uniquely assigned by the one set of the equal-length components a corresponding variable-length code and a code length of the variable-length code. Combination of the first and second equal-length components is preselected such that the maximum value of the absolute value of the first equal-length component increases as the absolute value of the second equal-length component combined therewith decreases. The second equal-length components are classified into a plurality of classes in accordance with the magnitude of the absolute value. Each address includes a first region having a value and a length uniquely specified based on the class including the second equal-length component, a second region storing the first equal-length component, and a third region storing the second equal-length component, and is constructed to have a fixed length as a whole. Region lengths of the second and third regions are determined correspondingly to the class including the second equal-length component, and each are specifically determined to have the minimum value required for storing the maximum values of the absolute values of the first and second equal-length components of the combinations of the equal-length components included in the corresponding class.

摘要翻译： 用于从由一组第一和第二等长分量形成的数据产生可变长度码的可变长度码表存储在由一组等长分量唯一分配的地址a相应的地址 可变长度代码和可变长度代码的代码长度。 预先选择第一和第二等长分量的组合，使得第一等长分量的绝对值的最大值随着与其组合的第二等长分量的绝对值减小而增加。 第二等长分量根据绝对值的大小被分类为多个类别。 每个地址包括具有基于包括第二等长分量的类别唯一地指定的值和长度的第一区域，存储第一等长分量的第二区域和存储第二等长分量的第三区域，以及 被构造为具有整体的固定长度。 对应于包括第二等长分量的类别确定第二和第三区域的区域长度，并且每个具体确定为具有存储第一和第二等长度的绝对值的最大值所需的最小值 相应类别中包括的等长分量组合的组成部分。

公开(公告)号：US5537551A

公开(公告)日：1996-07-16

申请号：US978344

申请日：1992-11-18

申请人： Jeffrey N. Denenberg ,  Edward D. Weinberger ,  Michael L. Gordon

发明人： Jeffrey N. Denenberg ,  Edward D. Weinberger ,  Michael L. Gordon

IPC分类号： H03M7/42 ,  H03M7/30 ,  G06F15/16 ,  H03M7/48

CPC分类号： H03M7/42

摘要： A method for compressing and subsequently decompressing digital data communicated in an interactive computer network, the network designed to provide informational and transactional services to a very large population of users. The method features steps for compressing bytes of network data before transmission by substituting variable-length code words obtained from a fixed, look-up table, and, reconstituting the bytes using a fixed, decompression look-up table when the code words are received at the data reception site. In accordance with the invention, the compression and decompression look-up tables are statistically compiled by sampling the occurrence frequency of byte pairs in the network data stream, and where byte pairs are found to occur above a predetermined frequency, code words having lengths inversely related to the occurrence frequency are created for inclusion in the table so that a code word may be substituted for one byte of a pair when the other byte of the pair is found to precede it during compression, and the byte reconstituted from the code word using the decompression table when the code word is received at the reception site. Additionally, where a byte and its preceding byte constitute a pair not found within the pairs compression table, the method features steps for transmitting the byte compressed in accordance with a context-free encoding scheme, together with a suitable escape code word. Yet further, the method features steps for combining other compression and decompression procedures with the byte-pair compression and decompression to produce a compound compression scheme for the network data stream.

摘要翻译： 一种用于压缩和随后解压缩在交互式计算机网络中传送的数字数据的方法，该网络被设计为向非常大的用户群体提供信息和事务服务。 该方法具有以下步骤：通过从固定的查找表中获取的可变长度码字来代替在发送之前压缩网络数据的字节，并且当代码字被接收到时，使用固定的解压缩查找表重新构建字节 数据接收站点。 根据本发明，压缩和解压缩查找表通过对网络数据流中的字节对的出现频率进行抽样来统计地编译，并且发现字节对在预定频率之上发生，具有长度相反的码字 创建发生频率以包括在表中，使得当在压缩期间发现该对的另一个字节在其前面时，代码字可以被替换成一对的一个字节，并且使用该代码字重新构成字节 在接收站点接收到码字时的解压缩表。 此外，在一个字节及其前一个字节构成在对压缩表中未找到的一个字节的情况下，该方法具有用于根据无上下文编码方案传送被压缩的字节与适当的转义码字的步骤。 此外，该方法具有将其他压缩和解压缩过程与字节对压缩和解压缩组合以产生网络数据流的复合压缩方案的步骤。

公开(公告)号：US5504484A

公开(公告)日：1996-04-02

申请号：US148326

申请日：1993-11-08

申请人： William B. Wilson

发明人： William B. Wilson

IPC分类号： H04N5/92 ,  H03M7/30 ,  H03M7/40 ,  H03M7/42 ,  H04N7/54 ,  H04N19/423 ,  H04N19/46 ,  H04N19/50 ,  H04N19/625 ,  H04N19/70 ,  H04N19/91

CPC分类号： H03M7/42 ,  H04N19/00 ,  H04N19/61 ,  H04N7/54 ,  H04N19/70

摘要： A variable-length data alignment apparatus receives header data and blocks from different sources, forms a header based on the received header data and outputs the header followed by blocks. The variable-length data alignment apparatus has a RAM for storing the header data, and a buffer for storing the blocks. A processor produces a plurality of commands and processes the header data from the RAM. The commands are prosecuted in a multiplexer and a bit stream coder to form a header and to append the blocks, stored in the buffer, after the header.

摘要翻译： 可变长度数据对准装置从不同的源接收标题数据和块，根据接收到的报头数据形成报头，并输出后跟块的报头。 可变长度数据对准装置具有用于存储标题数据的RAM和用于存储块的缓冲器。 处理器产生多个命令并从RAM处理头部数据。 这些命令在多路复用器和比特流编码器中被起诉以形成头部，并且在头部之后附加存储在缓冲器中的块。

公开(公告)号：US5488366A

公开(公告)日：1996-01-30

申请号：US134067

申请日：1993-10-12

申请人： Druong-Yow Wu

发明人： Druong-Yow Wu

IPC分类号： H03M7/42 ,  H03M7/40

CPC分类号： H03M7/425

摘要： The present invention comprises an apparatus for decoding an ordered sequence of incoming binary bit-stream in serial containing a plurality of variable length codewords with a maximum codeword length of M. The decoding apparatus comprises a serial to parallel converting and shifting means for receiving the incoming bit stream, and for receiving a shift-count for shifting and converting the shift-count number of bits for adding to a parallel data record. The decoding apparatus further comprises a dictionary means including at least two dictionary tables for listing a plurality of standard codewords wherein each of the dictionary tables having a bit-length less than M. The decoding apparatus further comprises a decoding means for decoding the parallel data record by utilizing the dictionary means and to generate the shift-count as an input to the serial to parallel converting and shifting means.

摘要翻译： 本发明包括一种用于解码串行输入的二进制比特流的有序序列的装置，其中包含具有最大码字长度M的多个可变长度码字。解码装置包括串行到并行转换和移位装置，用于接收进入 并且用于接收用于移位和转换用于添加到并行数据记录的位移计数位数的移位计数。 解码装置还包括字典装置，其包括用于列出多个标准码字的至少两个字典表，其中每个字节表的位长度小于M.解码装置还包括解码装置，用于解码并行数据记录 通过利用字典装置并产生移位计数作为串行到并行转换和移位装置的输入。

公开(公告)号：US5479527A

公开(公告)日：1995-12-26

申请号：US163872

申请日：1993-12-08

申请人： Yueh-Chang Chen

发明人： Yueh-Chang Chen

IPC分类号： G06T9/00 ,  H03M7/42 ,  H03M7/46 ,  H04N7/26 ,  H04N7/30 ,  G06K9/36 ,  G06K9/46

CPC分类号： H03M7/46 ,  H03M7/42 ,  H04N19/124 ,  H04N19/126 ,  H04N19/13 ,  H04N19/91

摘要： A variable length coder is disclosed having a ping-pong zigzag RAM, a zig-zag FIFO and a variable length integer (VLI), variable length code word (VLC) mixer. The ping-pong zig-zag RAM has a first RAM for processing each odd ordinalled block of the inputted sequence of blocks and a second RAM for processing each even ordinalled block of the inputted sequence of blocks. The zigzag FIFO has a comparator circuit, a counter and a FIFO. The comparator circuit is for determining whether or not an inputted coefficient is equal to zero. If the coefficient is non-zero, it is stored in the FIFO. If the coefficient equals zero, the counter increments a count maintained therein. The counter counts the number of zeros in each continuous sequence of zero coefficients in each block and outputs the count for each sequence of zeros for storage in the FIFO. The VLI,VLC mixer has a decoder for receiving the length of a VLC for each VLI,VLC pair and for outputting a mask word depending on the inputted VLC length. The VLI,VLC mixer also has a barrel shifter for receiving the VLI,VLC and VLC length. Using the mask word, the barrel shifter shifts the VLI to particular bit positions of a shifter register therein and inserts the VLC immediately adjacent to the shifted VLI.

摘要翻译： 公开了一种具有乒乓Z字形RAM，Z字形FIFO和可变长度整数（VLI），可变长度码字（VLC）混频器的可变长度编码器。 乒乓Z字形RAM具有用于处理输入的块序列的每个奇数序列块的第一RAM和用于处理输入的块序列的每个偶数序列块的第二RAM。 Z字形FIFO具有比较器电路，计数器和FIFO。 比较器电路用于确定输入的系数是否等于零。 如果系数不为零，则存储在FIFO中。 如果系数等于零，则计数器增加其中保留的计数。 计数器对每个块中零系数的每个连续序列中的零数进行计数，并输出每个零序列的计数，以存储在FIFO中。 VLI，VLC混频器具有解码器，用于为每个VLI，VLC对接收VLC的长度，并根据输入的VLC长度来输出掩码字。 VLI，VLC混频器还具有用于接收VLI，VLC和VLC长度的桶形移位器。 使用掩码字，桶形移位器将VLI移位到其中的移位寄存器的特定位位置，并将VLC插入到与移位的VLI相邻的位置。

公开(公告)号：US5473376A

公开(公告)日：1995-12-05

申请号：US347639

申请日：1994-12-01

申请人： Cheung Auyeung

发明人： Cheung Auyeung

IPC分类号： H03M7/42 ,  H04N7/26 ,  H04N7/30

CPC分类号： H03M7/42 ,  H04N19/60 ,  H04N19/13 ,  H04N19/91

摘要： The present invention is a method (100) and apparatus (300) for adaptive entropy encoding/decoding of a plurality of quantised transform coefficients in a video/image compression system. For encoding, first, a predetermined number of quantized transform coefficients are received in a predetermined order, giving a generally decreasing average power. Then the quantized transform coefficients are parsed into a plurality of coefficient groups. When the last coefficient group comprises all zero quantized coefficients, it is discarded. The coefficient groups are then converted into a plurality of parameter sets in the predetermined order. A current parameter set is obtained from the parameter sets in the reverse order of the predetermined order. A current entropy encoder is selected adaptively based on the previously selected entropy encoder and the previous parameter set. The current parameter set is encoded by the current entropy encoder to provide entropy encoded information bits.

摘要翻译： 本发明是用于对视频/图像压缩系统中的多个量化变换系数进行自适应熵编码/解码的方法（100）和装置（300）。 对于编码，首先，以预定顺序接收预定数量的量化变换系数，给出通常降低的平均功率。 然后将量化的变换系数解析为多个系数组。 当最后一个系数组包括所有零量化系数时，它被丢弃。 然后将系数组以预定顺序转换成多个参数组。 以预定顺序的相反顺序从参数集获得当前参数集。 基于先前选择的熵编码器和先前的参数集，自适应地选择当前熵编码器。 当前参数集由当前熵编码器编码以提供熵编码信息比特。

公开(公告)号：US5467088A

公开(公告)日：1995-11-14

申请号：US135448

申请日：1993-10-13

申请人： Shigenori Kinouchi ,  Akira Sawada

发明人： Shigenori Kinouchi ,  Akira Sawada

IPC分类号： G06T9/00 ,  H03M7/42 ,  H03M7/40

CPC分类号： H03M7/425 ,  G06T9/005

摘要： A huffman code decoding circuit has a memory storing a decoded word and a code length or a pointer to be accessed in the next time determined on the basis of a state transition upon decoding of a bit variable length code per every one or n bits and a flag representative of the decoding condition of the code and outputting the decoded word and the code length or the pointer for next access and the flag corresponding to an access address of m bits. A latching circuit latches the pointer of m-1 bit output from the memory when the flag is indicative of continuation of decoding, and is reset when the flag output from the memory is indicative of completion of decoding. A selector selectively outputs n-1 bit from one of the latching circuit and the bit variable length code to the memory, according to selection for decoding of the bit variable length code per every 1 bit or every n bit.

摘要翻译： 哈夫曼码解码电路具有存储器，存储存储解码字，以及在下一次基于每1位或n位对位可变长度码的解码时的状态转移确定的代码长度或指针，以及 代表代码的解码条件并输出解码的字和代码长度或下一次访问的指针和与m位的访问地址对应的标志。 当标志指示解码的继续时，锁存电路锁存从存储器输出的m-1位的指针，并且当从存储器输出的标志指示解码完成时，锁存电路被复位。 根据每1位或每n位对位可变长度码进行解码的选择，选择器选择性地将n-1位从锁存电路和位可变长度码中输出到存储器。