公开(公告)号：US4882624A

公开(公告)日：1989-11-21

申请号：US167141

申请日：1988-03-11

申请人： Hajime Sumiyoshi

发明人： Hajime Sumiyoshi

IPC分类号： H04N5/05 ,  H04N5/08 ,  H04N5/10

CPC分类号： H04N5/08

摘要： A synchronizing signal separation circuit for separating a composite synchronizing signal having a variable peak voltage subject to changes from a composite video signal, the composite synchronizing signal including a vertical synchronizing signal having a predetermined level for controlling vertical scanning in a television receiver. The separation circuit includes a composite separation circuit for separating the composite synchronizing signal from the composite video signal received from a source of video signals and a charge control circuit for maintaining the stability and the predetermined level of the vertical synchronizing signal after changes in synchronizing signal peak voltage.

摘要翻译： 一种同步信号分离电路，用于分离具有来自复合视频信号的变化的具有可变峰值电压的复合同步信号，所述复合同步信号包括具有用于控制电视接收机中的垂直扫描的预定电平的垂直同步信号。 分离电路包括复合分离电路，用于将复合同步信号与从视频信号源接收的复合视频信号和用于在同步信号峰值变化之后保持稳定性和垂直同步信号的预定电平的充电控制电路分离 电压。

公开(公告)号：US4858008A

公开(公告)日：1989-08-15

申请号：US249141

申请日：1988-09-26

申请人： Ulrich Sieben ,  Heinrich Schemmann

发明人： Ulrich Sieben ,  Heinrich Schemmann

IPC分类号： H04N5/06 ,  H04N5/10

CPC分类号： H04N5/10 ,  H04N5/06

摘要： A circuit is arranged to derive the internal vertical synchronizing signals and field identification signals for a digital television signal. The circuit operates from the internal horizontal synchronizing signals and the separated external synchronizing signals and employs a sign inverter, an accumulator, an absolute value device, a comparator, a counter and AND gates, as well as an OR gate. These components, as coupled, produce the above-noted signals by digital generation and requires no subcircuits that are independent of the horizontal oscillator which horizontal oscillator is arranged in a phase lock loop.

摘要翻译： 电路被布置成导出用于数字电视信号的内部垂直同步信号和场识别信号。 该电路由内部水平同步信号和分离的外部同步信号进行工作，并使用符号反相器，累加器，绝对值器件，比较器，计数器和与门，以及OR门。 耦合的这些部件通过数字生成产生上述信号，并且不需要独立于水平振荡器的子电路，水平振荡器被布置在锁相环中。

公开(公告)号：US4821098A

公开(公告)日：1989-04-11

申请号：US81386

申请日：1987-08-03

申请人： Wouter Smeulers

发明人： Wouter Smeulers

IPC分类号： H04N5/08 ,  H04N5/10

CPC分类号： H04N5/08

摘要： A circuit for deriving a synchronizing signal contained in an incoming video signal, having a pulse generator generating the synchronizing signal when the incoming signal reaches a threshold value. This treshold value corresponds to a level located between the peak and reference levels of the incoming signal and is determined with the aid of a keyed integrator, which integrates the video signal during a period of time which at least partly coincides with the occurrence of an incoming line synchronizing pulse and during a period of time after this occurrence, but before the end of the line blanking interval. In the synchronized state of the line synchronizing circuit, the required keying pulses are generated by this line synchronizing circuit; in the non-synchronized state the keying pulses are derived from the delayed output signal of the pulse generator. (FIG. 2).

摘要翻译： 用于导出包含在输入视频信号中的同步信号的电路，具有当输入信号达到阈值时产生同步信号的脉冲发生器。 该阈值对应于位于输入信号的峰值和参考电平之间的电平，并且借助于键控积分器来确定，该键控积分器在一段时间内对视频信号进行积分，该时间段至少部分地与出现的进入 在线路同步脉冲之间以及在该事件发生之后的一段时间内，但在行消隐间隔结束之前。 在线路同步电路的同步状态下，所需的键控脉冲由该线路同步电路产生; 在非同步状态下，键控脉冲从脉冲发生器的延迟输出信号导出。 （图2）。

公开(公告)号：US4789896A

公开(公告)日：1988-12-06

申请号：US141359

申请日：1987-12-11

申请人： Hiroyasu Kishi ,  Hiromi Arai

发明人： Hiroyasu Kishi ,  Hiromi Arai

IPC分类号： H04N5/10 ,  H04N5/08

CPC分类号： H04N5/10

摘要： The present invention relates to a vertical synchronizing pulse generating circuit in a television receiver, wherein a vertical synchronizing separation circuit (VS) is so composed not as to directly integrate pulses sequentially outputted from a composite synchronizing separation circuit, but as to integrate a small amount of electric current outputted according to the sequentially outputted pulses. Accordingly, it is possible to reduce the capacity of a capacitor (22) used for the integration and at the same time, it is possible to incorporate the capacitor in an integrated circuit, Thus, it is possible to decrease the number of pins provided to the integrated circuit. Furthermore, the small amount of electric current can be regulated according to the electric current flowing through an externally connected load (28).

公开(公告)号：US4774576A

公开(公告)日：1988-09-27

申请号：US829588

申请日：1986-02-13

申请人： Martin A. Lilley

发明人： Martin A. Lilley

IPC分类号： H04N5/10 ,  H04N7/04

CPC分类号： H04N5/10

摘要： A method and apparatus for producing a video composite blanking signal which provides for selectively unblanking lines of video information which would normally be blanked according to a predetermined television standard. Each line in a frame of video data is assigned a line type based on its location in the sequence of lines of video information. Those lines that are in the vertical blanking period are assigned a different line type than those which are not. In response to unblanking selection data, line types of lines which are normally blanked are selectively modified to the line types of those lines which are not normally modified. The vertical interval blanking signal is produced only for those line types for line in the vertical blanking period.

摘要翻译： 一种用于产生视频复合消隐信号的方法和装置，其提供根据预定的电视标准通常将被消隐的视频信息的选择性地非空白行。 视频数据帧中的每行基于其在视频信息的行​​序列中的位置被分配行类型。 在垂直消隐期间的那些行被分配不同于不是的行。 响应于非空白选择数据，通常消隐的行的行类型被选择性地修改为通常不被修改的那些行的行类型。 垂直间隔消隐信号仅在垂直消隐期间为线路类型生产。

公开(公告)号：US4757373A

公开(公告)日：1988-07-12

申请号：US928339

申请日：1986-11-07

申请人： Johannes H. J. M. Van Rooy

发明人： Johannes H. J. M. Van Rooy

IPC分类号： H04N5/14 ,  H03G7/00 ,  H04N5/20 ,  H04N9/68 ,  H04N5/10 ,  H04N9/64

CPC分类号： H03G7/00 ,  H04N5/20 ,  H04N9/68

摘要： The circuit has a gain factor characteristic curve with various breakpoints below which and above which a larger or a smaller gain factor, respectively, is present. Both the breakpoints and the gain factors above these points are variable dependent on the magnitude of the input signal. For picture signal processing for which the signal values below the breakpoints reach the output signal in an optimum way and above which an optimum adaptive white signal compression is present, the circuit is formed with a signal multiplier circuit (2) for multiplying a picture voltage (VI) and a first direct voltage (Va) by a control voltage (VR), and with a signal minimum detection circuit (4) for passing the lowest voltage value when the said picture voltage (VI) is applied relative to the voltage originating from the signal multiplier circuit (2) and relative to a second direct voltage (Vb), with the control voltage (VR) being derived from the voltage value that has been passed.

摘要翻译： 该电路具有各种断点的增益因子特性曲线，低于此值时，分别存在较大或较小的增益因子。 高于这些点的断点和增益因子都取决于输入信号的幅度。 对于图像信号处理，其中低于断点的信号值以最佳方式到达输出信号，并且其中存在最佳自适应白信号压缩，该电路形成有信号乘法器电路（2），用于将图像电压 VI）和通过控制电压（VR）的第一直流电压（Va），以及用于当施加所述图像电压（VI）时相对于源自所述图像电压（VI）的电压来传递最低电压值的信号最小检测电路（4） 信号乘法器电路（2）和相对于第二直流电压（Vb）的控制电压（VR），其中控制电压（VR）源自已经通过的电压值。

公开(公告)号：US4683495A

公开(公告)日：1987-07-28

申请号：US800890

申请日：1985-11-22

申请人： Thorsten Brock

发明人： Thorsten Brock

IPC分类号： H04N5/10 ,  H04N5/04

CPC分类号： H04N5/10

摘要： To distinguish between the two fields in a television signal, television synchronizing pulses are applied to a pulse interval detector. The output signal of the pulse interval detector assumes a first signal state when pulse intervals are measured which are located between first and second limit values, and a second signal state when the pulse intervals are outside these limit values. The pulse interval detector is connected to a time measuring element which counts the pulse intervals of the synchronizing pulse when the first signal state is present. The time measuring element produces a field identification signal in dependence on the fact whether, for example, the first signal state is present for a longer period of time for one field than for the other field.

摘要翻译： 为了区分电视信号中的两个场，电视同步脉冲被施加到脉冲间隔检测器。 当脉冲间隔被测量位于第一和第二极限值之间时，脉冲间隔检测器的输出信号呈现第一信号状态，当脉冲间隔在这些极限值之外时，第二信号状态。 脉冲间隔检测器连接到当存在第一信号状态时对同步脉冲的脉冲间隔进行计数的时间测量元件。 时间测量元件根据例如第一信号状态是否存在一个场的时间长于另一个场的事实来产生场识别信号。

公开(公告)号：US4680633A

公开(公告)日：1987-07-14

申请号：US726624

申请日：1985-04-24

申请人： Richard C. Gerdes ,  Peter R. Vokac

发明人： Richard C. Gerdes ,  Peter R. Vokac

IPC分类号： H04N5/10 ,  H04N5/16 ,  H04N5/04

CPC分类号： H04N5/16 ,  H04N5/10

摘要： A composite video signal is input to a DC restore circuit and a sync separator circuit, the output of which is connected to a sync decoder circuit. The DC restore circuit includes a negative sensing peak sample and hold circuit that generates a first reference voltage equal to the sync tip voltage. A first differential amplifier substracts the composite video signal from the reference voltage and produces an inverted, level shifted replica, the sync tip voltage of which is zero. A second differential amplifier having an output clamping circuit, in conjunction with a comparator, produces a composite sync voltage that is used to strobe a sample and hold circuit to produce a second reference voltage. The replica is inverted by a second differential amplifier that subtracts the replica from the second reference voltage to produce the DC restored video signal, a "back porch" portion of which is accurately referenced to zero volts.

摘要翻译： 复合视频信号被输入到DC恢复电路和同步分离器电路，其输出端连接到同步解码器电路。 DC恢复电路包括产生等于同步尖端电压的第一参考电压的负感测峰值采样和保持电路。 第一差分放大器将复合视频信号与参考电压相减，并产生反相电平移位副本，其同步尖端电压为零。 具有与比较器结合的输出钳位电路的第二差分放大器产生用于选通采样和保持电路以产生第二参考电压的复合同步电压。 复制品由第二差分放大器反相，该第二差分放大器从第二参考电压中减去副本以产生DC恢复的视频信号，“后沿”部分被准确地称为零伏特。

公开(公告)号：US4543614A

公开(公告)日：1985-09-24

申请号：US573228

申请日：1984-01-23

申请人： Keming J. Chen

发明人： Keming J. Chen

IPC分类号： H04N5/10 ,  H04N5/50 ,  H04N5/44 ,  H04N5/08

CPC分类号： H04N5/10 ,  H04N5/50

摘要： A video sync validity detector comprises a peak detector circuit and an average detector circuit both responsive to output signals from a sync separator network. Sync representative signals are provided from the output of the peak detector. The average detector is coupled to the peak detector for inhibiting sync representative outputs therefrom in the presence of sync separator output signals representative of false sync signals of average value.

摘要翻译： 视频同步有效性检测器包括响应于来自同步分离器网络的输出信号的峰值检测器电路和平均检测器电路。 从峰值检测器的输出提供同步代表信号。 在存在表示平均值的伪同步信号的同步分离器输出信号的情况下，平均检测器耦合到峰值检测器以禁止其代表性的输出。

公开(公告)号：US4520394A

公开(公告)日：1985-05-28

申请号：US490667

申请日：1983-05-02

申请人： Kenji Kaneko

发明人： Kenji Kaneko

IPC分类号： H04N5/93 ,  G11B20/10 ,  G11B27/30 ,  H03L7/08 ,  H04N5/06 ,  H04N5/10 ,  H04N5/932 ,  H04N5/04 ,  H04N7/04

CPC分类号： G11B20/10527 ,  G11B27/3054 ,  H03L7/0807 ,  H04N5/932

摘要： A horizontal scanning frequency multiplying circuit comprises a flip-flop supplied with an input horizontal synchronizing signal having a horizontal scanning frequency f.sub.H of a television signal, a phase-locked-loop (PLL) for producing a signal having a frequency Nf.sub.H (N is an integer over 1), a first counter supplied with an output signal of a voltage controlled oscillator within the PLL as a clock signal, for producing a counted output every time the clock signal is counted for a predetermined counting time T1 and supplying this counted output to the flip-flop to reset the flip-flop, a second counter supplied with the output signal of the voltage controlled oscillator as a clock signal, for counting this clock signal, a counted value setting circuit for producing a high-level output according to an output of the second counter when the second counter counts for a predetermined counting time T2, where T2>T1, and an OR-gate supplied with the input horizontal synchronizing signal and an output signal of the counted value setting circuit. The OR-gate supplies its output to the flip-flop to set the flip-flop and supplies its output to the second counter to reset the second counter.

摘要翻译： 水平扫描倍增电路包括提供有具有电视信号的水平扫描频率fH的输入水平同步信号的触发器，用于产生频率为NfH的信号的锁相环（PLL）（N为 整数超过1），第一计数器提供PLL内的压控振荡器的输出信号作为时钟信号，用于在每次在预定的计数时间T1计数时钟信号时产生计数输出，并将该计数输出提供给 触发器复位触发器，提供有压控振荡器的输出信号的第二计数器作为时钟信号，用于对该时钟信号进行计数;计数值设置电路，用于产生根据 当第二计数器计数预定计数时间T2时，第二计数器的输出，其中T2> T1，以及提供有输入水平同步信号的或门，以及o 计数值设定电路的输出信号。 或门将其输出提供给触发器以设置触发器并将其输出提供给第二计数器以复位第二计数器。