METHOD FOR MONITORING AN EXECUTION OF A PROGRAM CODE PORTION AND CORRESPONDING SYSTEM-ON-CHIP

    公开(公告)号:US20230342279A1

    公开(公告)日:2023-10-26

    申请号:US18306032

    申请日:2023-04-24

    CPC classification number: G06F11/3466 G06F11/3612

    Abstract: A method is provided for monitoring an execution of a selected program code portion stored in a memory address range between a start address and an end address. The method includes starting a timing when a program counter points to the start address of the selected program code portion. Current values of the program counter are compared with a set of target addresses specific to the selected program code portion including the end address of the selected program code portion. The timing is stopped when the program counter points to the end address of the selected program code portion. An error signal is generated in response to the timing duration being outside a nominal duration range specific to the selected program code portion.

    METHOD FOR EXECUTING A SOFTWARE PROGRAM BY A PROCESSING UNIT COMPRISING A COMPILATION PHASE

    公开(公告)号:US20230161863A1

    公开(公告)日:2023-05-25

    申请号:US18058130

    申请日:2022-11-22

    CPC classification number: G06F21/44

    Abstract: In an embodiment a method includes compiling, by a processor in a compiling phase, a software program intended to be executed by the processor, the processor having secure and non-secure access right level execution contexts, and/or privileged and non-privileged access right level execution contexts and generating, in the compilation phase, instructions in machine language having an exclusively secure access right level when the instructions are intended to be executed in the secure access right level execution context, and instructions having a non-privileged access right level when the instructions are intended to be executed in the non-privileged access right level execution context.

    METHOD, SYSTEM, AND DEVICE FOR SOFTWARE AND HARDWARE COMPONENT CONFIGURATION AND CONTENT GENERATION

    公开(公告)号:US20230078144A1

    公开(公告)日:2023-03-16

    申请号:US17898306

    申请日:2022-08-29

    Abstract: System, method, and circuitry for generating content for a programmable computing device based on user-selected configuration information. A settings registry is generated based on the user's selections. The settings registry and the user selected configuration information is utilized to generate the content, such as code, data, parameters, settings, etc. When the content is provided to the programmable computing device, the content initializes, configures, or controls one or more software and hardware aspects of the programmable computing device, such as boot sequence configurations, internal peripheral configurations, states of the programmable computing device, transitions between states of the programmable computing device, etc., and various combinations thereof.

    I2C communication
    127.
    发明授权

    公开(公告)号:US11580052B2

    公开(公告)日:2023-02-14

    申请号:US17003764

    申请日:2020-08-26

    Inventor: Yves Magnaud

    Abstract: The present disclosure relates to a communication method by I2C bus between a emitting device and a receiving device, in which: a rising edge of a clock signal of the I2C bus, directly following a start condition of an I2C communication, is recorded; and when an interruption is generated within the receiving device, the receiving device verifies whether the rising edge was recorded.

    METHOD FOR VERIFYING AN EXECUTION OF A SOFTWARE PROGRAM

    公开(公告)号:US20230040093A1

    公开(公告)日:2023-02-09

    申请号:US17882292

    申请日:2022-08-05

    Abstract: A method can be used for verifying an execution of a compiled software program stored in a program memory of a processor and executed by the processor. A write operation includes assigning a destination address in a register of the processor and writing a datum at a location pointed to by the destination address contained in the register. A verification operation includes reassigning the same destination address in the same register, reading the datum contained at the location pointed to by the destination address contained in the register after the reassignment, and comparing the read datum and the written datum.

    DC-DC CONVERTER WITH STEADY STATE CURRENT LIMITATION

    公开(公告)号:US20220393570A1

    公开(公告)日:2022-12-08

    申请号:US17679960

    申请日:2022-02-24

    Inventor: Lionel Cimaz

    Abstract: In an embodiment a current limiting circuit includes a circuit configured to detect when an input or output current of a DC to DC converter exceeds or falls below a threshold and a controller configured to store a first value representative of a level of an output voltage of the DC to DC converter in response to the input or output current exceeding or falling below a first threshold, store a second value representative of the level of the output voltage in response to the input or output current falling below a further threshold and modify a control signal based on the first and second values, wherein the control signal is modified based on the first and second values so that the control signal brings the output voltage to an intermediate voltage level between the level of the output voltage represented by the first value and the level of the output voltage represented by the second value.

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