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121.发明申请BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 64800 AND CODE RATE OF 7/15 AND QUADRATURE PHASE SHIFT KEYING, AND BIT INTERLEAVING METHOD USING SAME 有权用于低密度奇偶校验的位交换机检查长度为64800的长度和7/15的编码速率和相位相移键控和使用相同的位交互方法公开(公告)号：US20150214982A1
公开(公告)日：2015-07-30
申请号：US14606949
申请日：2015-01-27
Inventor： Sung-Ik PARK , Sun-Hyoung KWON , Jae-Young LEE , Heung-Mook KIM , Nam-Ho HUR
CPC classification number: H03M13/2792 , H03M13/1102 , H03M13/116 , H03M13/1185 , H03M13/255 , H03M13/2757 , H03M13/2778 , H03M13/616 , H03M13/6552 , H04L1/0041 , H04L1/0057 , H04L1/0058 , H04L1/0071 , H04L27/20 , H04L27/3416
Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 7/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation.
Abstract translation: 本文公开了一种位交织器，位交织编码调制（BICM）装置和比特交织方法。 比特交织器包括第一存储器，处理器和第二存储器。 第一存储器存储长度为64800且码率为7/15的低密度奇偶校验（LDPC）码字。 处理器通过基于比特组交织LDPC码字来产生交错码字。 位组的大小对应于LDPC码字的并行因子。 第二存储器将交织的码字提供给用于正交相移键控（QPSK）调制的调制器。
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122.发明申请SYSTEM AND METHOD FOR TRANSMITTING/RECEIVING THREE DIMENSIONAL VIDEO BASED ON DIGITAL BROADCASTING 审中-公开基于数字广播发送/接收三维视频的系统和方法公开(公告)号：US20130300825A1
公开(公告)日：2013-11-14
申请号：US13913811
申请日：2013-06-10
Inventor： Sung-Hoon KIM , Byung-Jun BAE , Kug-Jin YUN , Jae-Young LEE , Seung-Won KIM , Chung-Hyun AHN , Nam-Ho HUR , Soo-In LEE , Chieteuk AHN
IPC: H04N13/00
CPC classification number: H04N13/161 , H04H20/30 , H04H20/95 , H04N13/194 , H04N19/597 , H04N21/235 , H04N21/23614 , H04N21/2362 , H04N21/2365 , H04N21/4347 , H04N21/4348 , H04N21/435 , H04N21/845
Abstract: Provided is a system and method for transmitting and receiving 3D video based on digital broadcasting. The system includes: an encoder for generating 2D ES and 3D supplementary ES by encoding 2D video and 3D supplementary data; a packetizer for generating 2D video PES and 3D supplementary PES by packetizing the 2D video ES and the 3D supplementary ES; a PSI generator for generating a PSI; a TS generator for generating 2D video TS and 3D supplementary TS for the 2D video PES and the 3D supplementary PES; a multiplexer for multiplexing the transport streams to transmit the 2D video TS as a normal stream and transmit the 3D supplementary TS, the PSI TS and 3D video synch data TS as robust stream; and a modulator for modulating the multiplexed TS according to a DTV specification and transmitting the modulated TS.
Abstract translation: 提供了一种用于基于数字广播发送和接收3D视频的系统和方法。 该系统包括：通过编码2D视频和3D补充数据生成2D ES和3D补充ES的编码器; 用于通过打包2D视频ES和3D补充ES来生成2D视频PES和3D补充PES的打包器; 用于产生PSI的PSI发生器; 用于生成用于2D视频PES和3D补充PES的2D视频TS和3D辅助TS的TS生成器; 多路复用器，用于复用传输流以将2D视频TS作为普通流传输，并将3D补充TS，PSI TS和3D视频同步数据TS作为鲁棒流传输; 以及调制器，用于根据DTV规范调制经复用的TS，并发送调制的TS。
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123.发明公开公开(公告)号：US20240214112A1
公开(公告)日：2024-06-27
申请号：US18540654
申请日：2023-12-14
Inventor： Jae-Hyun SEO , Hoi-Yoon JUNG , Sung-Ik PARK , Bo-Mi LIM , Dong-Joon CHOI , Nam-Ho HUR
CPC classification number: H04L1/0041 , H04L1/0071 , H04L5/0053 , H04L2001/0093
Abstract: Disclosed herein are a method for processing a retransmission broadcast signal using multi-antenna signals based on channel bonding and an apparatus for the same. The apparatus includes a stream multiplexing (muxing) unit for generating a single piece of input data from signals received from two or more reception channels, an input formatting unit for converting the input data into a Physical Layer Pipe (PLP), a stream partitioning unit for segmenting the physical layer pipe into pieces of data to be respectively transmitted over two or more transmission channels, and two or more retransmission-signal-processing units for retransmitting the pieces of data to the respective transmission channels corresponding thereto through multiple transmission antennas.
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公开(公告)号：US20240171197A1
公开(公告)日：2024-05-23
申请号：US18429127
申请日：2024-01-31
Inventor： Sung-Ik PARK , Sun-Hyoung KWON , Jae-Young LEE , Heung-Mook KIM , Nam-Ho HUR
CPC classification number: H03M13/2757 , H03M13/1102 , H03M13/116 , H03M13/1185 , H03M13/255 , H03M13/2778 , H03M13/2792 , H03M13/616 , H03M13/6552 , H04L1/0041 , H04L1/0057 , H04L1/0058 , H04L1/0071 , H04L27/20 , H04L27/3416
Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 7/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation.
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公开(公告)号：US20240015208A1
公开(公告)日：2024-01-11
申请号：US18188229
申请日：2023-03-22
Inventor： Hoi-Yoon JUNG , Sung-Ik PARK , Nam-Ho HUR , David Gomez-Barquero , Carlos Barjau Estevan
IPC: H04L67/1021 , H04L69/164 , H04L69/08
CPC classification number: H04L67/1021 , H04L69/164 , H04L69/08
Abstract: Disclosed herein are a content provision method and apparatus using a convergence network. The content provision method may include creating a Quick UDP Internet Connections V1 (QUICV1) path with User Equipment (UE) through a Fifth-Generation (5G) core, when content satisfies a preset condition while the content is being provided to the UE through the QUICV1 path, determining to offload the content through the 5G core, creating an Internet Protocol Security (IPSEC) tunnel with an Advanced Television Systems Committee (ATSC) gateway (GW) through the 5G core, generating a QUIC multicast stream, providing QUIC multicast session information to multiple UE devices, and providing the content to multiple UE devices, for which a mode switches from a QUICV1 mode to a QUIC multicast mode, through the ATSC GW.
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Patent Agency Ranking
公开(公告)号：US20230283323A1
公开(公告)日：2023-09-07
申请号：US18177623
申请日：2023-03-02
Inventor： Bo-Mi LIM , Sung-Ik PARK , Sung-Jun AHN , Hoi-Yoon JUNG , Hae-Chan KWON , Nam-Ho HUR
IPC: H04B7/0413 , H04B7/08
CPC classification number: H04B7/0413 , H04B7/0811
Abstract: Disclosed herein are a broadcast signal transmission method for signaling a transmission structure based on a combination of LDM technology and MIMO technology and an apparatus using the same. The broadcast signal transmission method may include generating first signaling information, indicating a transmission structure based on a combination of Multiple-Input Multiple-Output (MIMO) technology and Layered Division Multiplexing (LDM) technology, for a first subframe of a current broadcast signal frame, generating second signaling information, indicating a transmission structure based on a combination of the MIMO technology and the LDM technology, for a current subframe subsequent to the first subframe, and generating a broadcast signal using the first signaling information and the second signaling information.
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公开(公告)号：US20220394117A1
公开(公告)日：2022-12-08
申请号：US17886167
申请日：2022-08-11
Inventor： Bo-Mi LIM , Sung-Ik PARK , Sun-Hyoung KWON , Jae-Young LEE , Heung-Mook KIM , Nam-Ho HUR
IPC: H04L69/324
Abstract: An apparatus for generating broadcast signal frame according to an embodiment of the present invention includes a combiner configured to generate a multiplexed signal by combining a core layer signal and an enhanced layer signal; a power normalizer configured to reduce power of the multiplexed signal to a power level corresponding to the core layer signal; a time interleaver configured to generate a time-interleaved signal by performing time-interleaving that is applied to both the core layer signal and the enhanced layer signal; and a frame builder configured to generate a broadcast signal frame including a preamble for signaling start position information and size information for each of Physical Layer Pipes (PLPs). In this case, the Physical Layer Pipes include a core layer physical layer pipe corresponding to the core layer signal and an enhanced layer physical layer pipe corresponding to the enhanced layer signal.
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公开(公告)号：US20220329264A1
公开(公告)日：2022-10-13
申请号：US17845614
申请日：2022-06-21
Inventor： Sung-Ik PARK , Sun-Hyoung KWON , Jae-Young LEE , Heung-Mook KIM , Nam-Ho HUR
Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 7/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation.
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公开(公告)号：US20220006474A1
公开(公告)日：2022-01-06
申请号：US17479763
申请日：2021-09-20
Inventor： Sung-Ik PARK , Sun-Hyoung KWON , Jae-Young LEE , Heung-Mook KIM , Nam-Ho HUR
Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 4096-symbol mapping.
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公开(公告)号：US20210377318A1
公开(公告)日：2021-12-02
申请号：US17314276
申请日：2021-05-07
Inventor： Hoi-Yoon JUNG , Sung-Ik PARK , Heung-Mook KIM , Nam-Ho HUR , David Gomez-Barquero , Eduardo Garro , Carlos Barjau Estevan
Abstract: Disclosed herein is an integrated core network of 5G and ATSC 3.0. The integrated core network of 5G and ATSC 3.0 includes multiple control plane entities and a user plane entity, and further includes an ATSC 3.0 gateway, thereby enabling multimedia content transmitted from the ATSC 3.0 gateway to the user plane entity under the control of the control entity to be delivered to user equipment over an ATSC 3.0 terrestrial network. The ATSC 3.0 gateway may include an ATSC 3.0 Control Plane Gateway (CP-GW) connected between the user plane entity and the multiple control plane entities and an ATSC 3.0 User Plane Gateway (UP-GW) connected to the user plane entity.
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