公开(公告)号：US07821294B2

公开(公告)日：2010-10-26

申请号：US12135249

申请日：2008-06-09

申请人： Susan K. Lichtensteiger ,  Michael R. Ouellette ,  Raymond W. M. Schuppe ,  Sebastian T. Ventrone

发明人： Susan K. Lichtensteiger ,  Michael R. Ouellette ,  Raymond W. M. Schuppe ,  Sebastian T. Ventrone

IPC分类号： H03K19/173

CPC分类号： H03K19/0008 ,  H03K19/173

摘要： Multi-state restore circuitry that allows storage elements of a power-managed functional block to be loaded when the functional block is repowered up so that the functional block is ready for operation virtually immediately after voltage ramp-up of the functional block. The multi-state restore circuitry includes a restore-state detector for determining which one of a plurality of restore states of the functional block is applicable to a particular repowering-up of the functional block. The multi-state restore circuitry also includes restore logic that loads the storage elements as a function of the restore state determined by the restore-state detector.

摘要翻译： 多功能恢复电路，允许在功能块被重新加电时加载功率管理功能块的存储元件，使得功能块在功能块的电压升高之后实际上准备好运行。 多状态恢复电路包括恢复状态检测器，用于确定功能块的多个恢复状态中的哪一个可应用于功能块的特定重新启动。 多状态恢复电路还包括根据由恢复状态检测器确定的恢复状态来加载存储元件的恢复逻辑。

公开(公告)号：US07752355B2

公开(公告)日：2010-07-06

申请号：US10832658

申请日：2004-04-27

申请人： Emory D. Keller ,  Anthony J. Perri ,  Sebastian T. Ventrone

发明人： Emory D. Keller ,  Anthony J. Perri ,  Sebastian T. Ventrone

IPC分类号： G06F5/00

CPC分类号： G06F13/4059

摘要： An asynchronous data transfer interface is provided across a boundary that allows high bandwidth data transfers which are packet based as defined by PCI_Express architecture, and has general utility in processor-based applications like servers, desktop applications, and mobile applications. A shared set of multi-port RAM buffers allow both an application layer AL and a transaction layer TL access to a communication protocol layer in a defined process that allows both the application layer AL and the transaction layer TL to read and manage the buffers in a 16 byte boundary in a manner that allows a data credit to be decoupled from a header credit.

摘要翻译： 跨越边界提供异步数据传输接口，允许高速带宽数据传输，这些数据传输是由PCI_Express架构定义的基于分组的，并且在基于处理器的应用程序（如服务器，桌面应用程序和移动应用程序）中具有通用功能。 共享的一组多端口RAM缓冲器允许应用层AL和事务层TL在定义的过程中访问通信协议层，允许应用层AL和事务层TL两者读取和管理缓冲区中的缓冲区 16字节边界以允许从标题信用中分离数据信用的方式。

公开(公告)号：US07750670B2

公开(公告)日：2010-07-06

申请号：US12185467

申请日：2008-08-04

申请人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Christopher B. Reynolds ,  Jack R. Smith ,  Sebastian T. Ventrone

发明人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Christopher B. Reynolds ,  Jack R. Smith ,  Sebastian T. Ventrone

IPC分类号： H03K19/173

CPC分类号： H03K19/17752 ,  G06F15/7867 ,  H03K19/17756 ,  H03K19/1776

摘要： A reconfigurable logic array (RLA) having a logic capacity and configured to process a function having a total logic requirement that exceeds the logic capacity of the RLA. The RLA includes first and second storage regions and a plurality of programmable logic elements located between the first and second storage regions. When the function is parsed into a plurality of functional blocks, this configuration allows the RLA to process the function by sequentially processing the functional blocks in alternating directions within the RLA, using the plurality of programmable logic elements to sequentially process each of the functional blocks and using the first and second storage regions to temporarily hold the input and output for that one of the functional blocks.

摘要翻译： 具有逻辑容量并被配置为处理具有超过RLA的逻辑容量的总逻辑要求的功能的可重构逻辑阵列（RLA）。 RLA包括第一和第二存储区域以及位于第一和第二存储区域之间的多个可编程逻辑元件。 当功能被解析成多个功能块时，该配置允许RLA通过在RLA内沿交替方向依次处理功能块来处理功能，使用多个可编程逻辑元件来顺序地处理每个功能块和 使用第一和第二存储区域临时保持该功能块的输入和输出。

公开(公告)号：US07732949B2

公开(公告)日：2010-06-08

申请号：US11550573

申请日：2006-10-18

申请人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Sebastian T. Ventrone ,  Keith R. Williams

发明人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Sebastian T. Ventrone ,  Keith R. Williams

IPC分类号： G05F3/06 ,  G06F1/00

CPC分类号： C09K11/77 ,  G06F1/3203

摘要： A system and method of predicting power events in intermittent power environments and dispatching computational operations of an integrated circuit accordingly. A power management prediction system includes a controller executing a prediction algorithm, an arrangement of computation circuitry, a non-volatile storage device containing a power requirements log and a power history log, a clock generator, an intermittent power source, and a power monitor circuit. A method of predicting intermittent power events and dispatching computational operations includes: storing power requirements of each computational operation, monitoring the intermittent power source to generate a history log, predicting a subsequent power event based on the history log, retrieving actual power requirements of one or more computational operations, comparing the predicted power event with actual power requirements, determining whether actual power requirements are satisfied, dispatching one or more computational operations that correspond to one or more actual power events, or performing an error recovery operation.

摘要翻译： 一种在间歇电力环境中预测电力事件并相应地调度集成电路的计算操作的系统和方法。 功率管理预测系统包括执行预测算法的控制器，计算电路的布置，包含电力需求日志和电力历史记录的非易失性存储装置，时钟发生器，间歇电源和功率监视电路 。 一种预测间歇功率事件和调度计算操作的方法包括：存储每个计算操作的功率需求，监测间歇电源以生成历史日志，基于历史日志预测随后的功率事件，检索一个或者 更多的计算操作，将预测功率事件与实际功率需求进行比较，确定是否满足实际功率需求，调度与一个或多个实际功率事件相对应的一个或多个计算操作，或执行错误恢复操作。

公开(公告)号：US20090240452A1

公开(公告)日：2009-09-24

申请号：US12053705

申请日：2008-03-24

申请人： Theodoros E. Anemikos ,  Phillip L. Corson ,  Mete Erturk ,  Ezra D.B. Hall ,  Anthony J. Perri ,  Sebastian T. Ventrone

发明人： Theodoros E. Anemikos ,  Phillip L. Corson ,  Mete Erturk ,  Ezra D.B. Hall ,  Anthony J. Perri ,  Sebastian T. Ventrone

IPC分类号： G01R23/16

CPC分类号： H04Q9/00 ,  H01L22/12 ,  H01L22/14 ,  H01L22/26 ,  H01L23/64 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed are embodiments of a system and a method that allow for wireless and dynamic intra-process (i.e., during and/or between process steps) measurements of integrated circuit parameters. The embodiments incorporate the use of a passive circuit, such as an inductor-capacitor-resistor (LCR) circuit resonator, that has a predetermined sensitivity to process variations in one or more physical or electrical integrated circuit parameters. The passive circuit can be wirelessly interrogated between and/or process steps. Then, the actual behavior exhibited by the passive circuit in response to the interrogation is compared to the expected behavior of an optimal circuit in the absence of process variations in order to determine the one or more parameters. Also disclosed is an embodiment of an exemplary passive circuit that can be used to implement the disclosed system and method embodiments.

摘要翻译： 公开了允许集成电路参数的无线和动态内部处理（即，在处理步骤期间和/或之间）的系统和方法的实施例。 这些实施例结合了对一个或多个物理或电气集成电路参数中的过程变化具有预定灵敏度的无源电路（例如电感器 - 电容 - 电阻（LCR）电路谐振器）的使用。 无源电路可以在和/或处理步骤之间进行无线询问。 然后，将无源电路响应于询问所表现的实际行为与没有过程变化的最佳电路的预期行为进行比较，以便确定一个或多个参数。 还公开了可用于实现所公开的系统和方法实施例的示例性无源电路的实施例。

公开(公告)号：US20090125744A1

公开(公告)日：2009-05-14

申请号：US11938899

申请日：2007-11-13

申请人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Sebastian T. Ventrone ,  Keith R. Williams

发明人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Sebastian T. Ventrone ,  Keith R. Williams

IPC分类号： G06F1/28

CPC分类号： G06F1/3203 ,  G06F1/3287 ,  Y02D10/171

摘要： A design structure for a system and method of predicting power events in intermittent power environments and dispatching computational operations of an integrated circuit accordingly. A power management prediction system includes a controller executing a prediction algorithm, an arrangement of computation circuitry, a non-volatile storage device containing a power requirements log and a power history log, a clock generator, an intermittent power source, and a power monitor circuit. A method of predicting intermittent power events and dispatching computational operations includes: storing power requirements of each computational operation, monitoring the intermittent power source to generate a history log, predicting a subsequent power event based on the history log, retrieving actual power requirements of one or more computational operations, comparing the predicted power event with actual power requirements, determining whether actual power requirements are satisfied, dispatching one or more computational operations that correspond to one or more actual power events, or performing an error recovery operation.

摘要翻译： 一种用于系统的设计结构以及在间歇电力环境中预测电力事件并相应地调度集成电路的计算操作的方法。 功率管理预测系统包括执行预测算法的控制器，计算电路的布置，包含电力需求日志和电力历史记录的非易失性存储装置，时钟发生器，间歇电源和功率监视电路 。 一种预测间歇功率事件和调度计算操作的方法包括：存储每个计算操作的功率需求，监测间歇电源以生成历史日志，基于历史日志预测随后的功率事件，检索一个或者 更多的计算操作，将预测功率事件与实际功率需求进行比较，确定是否满足实际功率需求，调度与一个或多个实际功率事件相对应的一个或多个计算操作，或执行错误恢复操作。

公开(公告)号：US07495492B2

公开(公告)日：2009-02-24

申请号：US11530981

申请日：2006-09-12

申请人： Pascal A. Nsame ,  Anthony J. Perri ,  Lansing U. Pickup ,  Sebastian T. Ventrone ,  Matthew R. Walland

发明人： Pascal A. Nsame ,  Anthony J. Perri ,  Lansing U. Pickup ,  Sebastian T. Ventrone ,  Matthew R. Walland

IPC分类号： H03K3/289

CPC分类号： G11C5/141 ,  G11C5/143 ,  G11C14/00

摘要： The invention comprises a dynamic voltage state-saving latch electrical circuit comprising a charge device adapted as a storage element, an integrated recovery mechanism, a supply voltage rail connected to the charge device, a hold signal allocated to the integrated recovery mechanism, a data signal input allocated to said charge device, a data signal output distributed from the charge device, and a clock signal allotted to the charge device, wherein said integrated recovery mechanism maintains a state of the charge device independent of the charge device.

摘要翻译： 本发明包括一种动态电压状态保存锁存电路，其包括适于作为存储元件的充电装置，集成恢复机构，连接到充电装置的电源电压轨，分配给集成恢复机构的保持信号，数据信号 分配给所述充电装置的输入，从所述充电装置分配的数据信号以及分配给所述充电装置的时钟信号，其中所述集成恢复机构保持所述充电装置的状态而与所述充电装置无关。

公开(公告)号：US20090024862A1

公开(公告)日：2009-01-22

申请号：US11779432

申请日：2007-07-18

申请人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Sebastian T. Ventrone ,  Keith Williams ,  Charles S. Woodruff

发明人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Sebastian T. Ventrone ,  Keith Williams ,  Charles S. Woodruff

IPC分类号： G06F1/30

CPC分类号： G06F1/3203

摘要： A method and structure to optimize computational efficiency in a low-power environment. The method includes determining an optimal point for maximizing computational efficiency in a low-power environment, and selectively controlling operation of at least one processing unit of a plurality of processing units in accordance with the determined optimal point. The structure includes a plurality of processing units, a load manager controlling selective parallel operation of at least one processing unit of the plurality of processing units, and an unregulated power source.

摘要翻译： 一种在低功耗环境下优化计算效率的方法和结构。 该方法包括确定用于在低功率环境中最大化计算效率的最佳点，以及根据所确定的最佳点选择性地控制多个处理单元中的至少一个处理单元的操作。 该结构包括多个处理单元，控制多个处理单元中的至少一个处理单元的选择性并行操作的负载管理器和未调节的电源。

公开(公告)号：US20080320423A1

公开(公告)日：2008-12-25

申请号：US11873754

申请日：2007-10-17

申请人： Elie Awad ,  Mariette Awad ,  Adam E. Trojanowski ,  Sebastian T. Ventrone

发明人： Elie Awad ,  Mariette Awad ,  Adam E. Trojanowski ,  Sebastian T. Ventrone

IPC分类号： G06F17/50

CPC分类号： G06F21/567

摘要： A system and method for protecting computing systems, and more particularly a system and method which a dedicated hardware component configured to communicate with a protection program. A computer hardware subsystem includes a memory comprising content. The content is at least a list of files which have been modified within a predetermined period of time. The list of files is a subset of files of a hard drive. A dedicated hardware component is configured to track the files which have been modified and provide a location of the files to the memory. A communication link between the dedicated hardware component and a protection program provides the protection program with the subset of files of the hard drive as referenced by the memory content. The invention is also directed to a design structure on which a circuit resides.

摘要翻译： 一种用于保护计算系统的系统和方法，更具体地，涉及配置成与保护程序进行通信的专用硬件组件的系统和方法。 计算机硬件子系统包括包含内容的存储器。 内容至少是在预定时间段内被修改的文件的列表。 文件列表是硬盘驱动器文件的一部分。 专用硬件组件被配置为跟踪已被修改的文件并且将文件的位置提供给存储器。 专用硬件组件和保护程序之间的通信链路为保护程序提供硬盘驱动器的文件的子集，如存储器内容所引用的。 本发明还涉及电路所在的设计结构。

公开(公告)号：US20080256503A1

公开(公告)日：2008-10-16

申请号：US11876076

申请日：2007-10-22

申请人： Kenneth J. GOODNOW ,  Clarence R. Ogilvie ,  Christopher B. Reynolds ,  Sebastian T. Ventrone ,  Keith R. Williams

发明人： Kenneth J. GOODNOW ,  Clarence R. Ogilvie ,  Christopher B. Reynolds ,  Sebastian T. Ventrone ,  Keith R. Williams

IPC分类号： G06F17/50

CPC分类号： H03K3/0315

摘要： A method and system for modulating logic clock oscillator frequency based on voltage supply. The system comprises a logic unit having a logic operation and a device to produce self-adjusting clocks to match the logic operation. The device is configured to use supply voltage as an independent variable to optimize device parameters for voltage variations. The invention is also directed to a design structure on which a circuit resides.

摘要翻译： 一种基于电压源调制逻辑时钟振荡器频率的方法和系统。 该系统包括具有逻辑操作的逻辑单元和用于产生自适应时钟以匹配逻辑运算的装置。 该器件被配置为使用电源电压作为独立变量来优化电压变化的器件参数。 本发明还涉及电路所在的设计结构。