公开(公告)号：US20190356517A1

公开(公告)日：2019-11-21

申请号：US16526433

申请日：2019-07-30

Applicant: Micron Technology, Inc.

Inventor： Raghukiran Sreeramaneni ,  Daniel B. Penney

IPC: H04L25/03 ,  H04L25/49 ,  G11C7/10 ,  G11C11/4096 ,  G11C7/02

Abstract: A device includes a voltage generator that generates a reference signal, a multi-level bias generator coupled to the voltage generator to receive the reference signal and generate a plurality of bias level signals based at least in part on the reference signal. The multi-level bias generator transmits the plurality of bias level signals to a plurality of multiplexers that each receive a select signal to select a subset of bias level signals of the plurality of bias level signals based. The device also includes an adjustment circuit of a decision feedback equalizer that receives a respective selected subset of bias level signals from one multiplexer of the plurality of multiplexers and utilizes the respective selected subset of bias level signals to compensate for inter-symbol interference of a bit due to a previously received bit of a bit stream.

公开(公告)号：US10482946B2

公开(公告)日：2019-11-19

申请号：US16448841

申请日：2019-06-21

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney

IPC: G11C11/4093 ,  G11C11/4076 ,  G11C11/4096 ,  G11C11/408

Abstract: Memory devices coupled to host devices may receive clocking signals and data strobe signals during write operations, which may present a skew. Memory specifications may include Write Preambles, preambles in the data signal provided at the beginning of write operations. Memory devices that decode particular features in the preamble, and that may relax the skew tolerances are provided. The memory devices may include configurable decoders that may be adjusted based on the features in the preamble or the preamble type. For example, memory devices may employ a rising edge, a falling edge, a low level, or a high level based on the specific type of preamble. Skew tolerances between the clock and the data strobe signals may be further improved by employing early write command launch points, using a training mechanism.

公开(公告)号：US10482936B2

公开(公告)日：2019-11-19

申请号：US16423852

申请日：2019-05-28

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney

IPC: G11C7/00 ,  G11C7/22 ,  G11C7/10

Abstract: Methods and systems that may employ adjustments to the latencies in the input circuitry to reduce the latency during initialization period and to prevent undesired effects from metastability are provided. Disclosed systems may employ adjustable delays during a signal training process to cause adjustments in the timing of the host that will reduce latencies during write cycles. Certain systems may further reduce latencies by employing input logic circuitry that produces a valid, consistent signal from the bidirectional connection, such as a gate, and preventing metastability in input circuitry altogether. Such circuitry allows bypassing of initialization periods to stabilize the input, and allows further reduction of the initialization.

公开(公告)号：US20190279694A1

公开(公告)日：2019-09-12

申请号：US16423852

申请日：2019-05-28

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney

IPC: G11C7/22 ,  G11C7/10

Abstract: Methods and systems that may employ adjustments to the latencies in the input circuitry to reduce the latency during initialization period and to prevent undesired effects from metastability are provided. Disclosed systems may employ adjustable delays during a signal training process to cause adjustments in the timing of the host that will reduce latencies during write cycles. Certain systems may further reduce latencies by employing input logic circuitry that produces a valid, consistent signal from the bidirectional connection, such as a gate, and preventing metastability in input circuitry altogether. Such circuitry allows bypassing of initialization periods to stabilize the input, and allows further reduction of the initialization.

公开(公告)号：US10366737B2

公开(公告)日：2019-07-30

申请号：US15850744

申请日：2017-12-21

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney

IPC: G11C11/4093 ,  G11C11/4076 ,  G11C11/4096 ,  G11C11/408

Abstract: Memory devices coupled to host devices may receive clocking signals and data strobe signals during write operations, which may present a skew. Memory specifications may include Write Preambles, preambles in the data signal provided at the beginning of write operations. Memory devices that decode particular features in the preamble, and that may relax the skew tolerances are provided. The memory devices may include configurable decoders that may be adjusted based on the features in the preamble or the preamble type. For example, memory devices may employ a rising edge, a falling edge, a low level, or a high level based on the specific type of preamble. Skew tolerances between the clock and the data strobe signals may be further improved by employing early write command launch points, using a training mechanism.

公开(公告)号：US20190222445A1

公开(公告)日：2019-07-18

申请号：US16191169

申请日：2018-11-14

Applicant: Micron Technology, Inc.

Inventor： Raghukiran Sreeramaneni ,  Daniel B. Penney

IPC: H04L25/03 ,  H04L25/49 ,  G11C7/10

CPC classification number: H04L25/03057 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/1063 ,  G11C11/4096 ,  G11C2207/107 ,  H04L25/4917

Abstract: A device includes a voltage generator that generates a reference signal, a multi-level bias generator coupled to the voltage generator to receive the reference signal and generate a plurality of bias level signals based at least in part on the reference signal. The multi-level bias generator transmits the plurality of bias level signals to a plurality of multiplexers that each receive a select signal to select a subset of bias level signals of the plurality of bias level signals based. The device also includes an adjustment circuit of a decision feedback equalizer that receives a respective selected subset of bias level signals from one multiplexer of the plurality of multiplexers and utilizes the respective selected subset of bias level signals to compensate for inter-symbol interference of a bit due to a previously received bit of a bit stream.

公开(公告)号：US20190221244A1

公开(公告)日：2019-07-18

申请号：US16360685

申请日：2019-03-21

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Harish N. Venkata ,  Guy S. Perry

IPC: G11C7/10 ,  G11C11/4096 ,  G11C11/4091

CPC classification number: G11C7/1006 ,  G11C7/1036 ,  G11C11/4091 ,  G11C11/4096 ,  G11C2211/4013

Abstract: The present disclosure includes apparatuses and methods related to shifting data. An example apparatus comprises sensing circuitry including a sense amplifier and a compute component having a first storage location and a second storage location associated therewith. A controller is coupled to the sensing circuitry. The controller is configured to control an amount of power associated with shifting a data value stored in the first storage location to the second storage location by applying a charge sharing operation.

公开(公告)号：US20190164593A1

公开(公告)日：2019-05-30

申请号：US15826236

申请日：2017-11-29

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  David R. Brown ,  Gary L. Howe

IPC: G11C11/4093 ,  G11C11/4076

CPC classification number: G11C11/4093 ,  G11C7/1093 ,  G11C7/1096 ,  G11C11/4076 ,  G11C2207/2254

Abstract: A memory device includes a data write circuitry. The data write circuitry is configured to capture a first write command received via an external input/output (I/O) interface. The data write circuitry is further configured to generate a first internal write start (InternalWrStart) in a data strobe (DQS) domain after capture of the first write command. The data write circuitry is additionally configured to write a first one or more data bits into at least one memory bank based on the first InternalWrStart, wherein the first InternalWrStart is generated internally in the memory device.

公开(公告)号：US20190122742A1

公开(公告)日：2019-04-25

申请号：US16049411

申请日：2018-07-30

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  William C. Waldrop

IPC: G11C17/18 ,  G11C17/16 ,  H04L9/08 ,  G11C17/08

Abstract: A memory device includes a memory array of a set of memory cells. Each memory cell of the set of memory cells includes at least one transistor and at least one capacitor. The memory array includes at least one programmed memory cell. The programmed memory cell is selectively programmed by applying hot-carrier injection (HCI) to a transistor of the programmed memory cell. The programmed memory cell may provide an indication of pattern data that may be used to facilitate functionality such as data encryption, data decryption, implementation of a particular memory device operation mode, and/or machine-implemented instructions.

公开(公告)号：US20180261264A1

公开(公告)日：2018-09-13

申请号：US15978578

申请日：2018-05-14

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Harish N. Venkata ,  Guy S. Perry

IPC: G11C7/10 ,  G11C11/4091 ,  G11C11/4096

CPC classification number: G11C7/1006 ,  G11C7/1036 ,  G11C11/4091 ,  G11C11/4096 ,  G11C2211/4013

Abstract: The present disclosure includes apparatuses and methods related to shifting data. An example apparatus comprises sensing circuitry including a sense amplifier and a compute component having a first storage location and a second storage location associated therewith. A controller is coupled to the sensing circuitry. The controller is configured to control an amount of power associated with shifting a data value stored in the first storage location to the second storage location by applying a charge sharing operation.