公开(公告)号：US20210342206A1

公开(公告)日：2021-11-04

申请号：US17373667

申请日：2021-07-12

Applicant: Micron Technology, Inc.

Inventor： Michael Sheperek ,  Larry J. Koudele ,  Bruce A. Liikanen

IPC: G06F11/07 ,  G11C16/08 ,  G11C16/28 ,  G11C16/10

Abstract: One or more of multiple metrics for multiple logical page types of the memory device are determined. Each of the metrics is indicative of a number of bit errors associated with a particular logical page type of the multiple logical page types. A current page margin associated with a first logical page type of the multiple logical page types is modified to determine a modified page margin based at least in part on a ratio using one or more of the multiple metrics. The current page margin associated with the first logical page type is adjusted in accordance with the modified page margin.

公开(公告)号：US20210334035A1

公开(公告)日：2021-10-28

申请号：US17316612

申请日：2021-05-10

Applicant: Micron Technology, Inc.

Inventor： Michael Sheperek ,  Larry J. Koudele ,  Bruce A. Liikanen

IPC: G06F3/06

Abstract: A data structure that identifies a characteristic of a region that is located between programming distributions of the memory device and that corresponds to read level thresholds at the region is determined. An estimator type is selected from a plurality of estimator types corresponding with the data structure. A read level threshold of the read level thresholds is estimated using the selected estimator type. A read operation is performed at the memory device using the read level threshold estimated using the selected estimator type.

公开(公告)号：US11119848B2

公开(公告)日：2021-09-14

申请号：US16507500

申请日：2019-07-10

Applicant: Micron Technology, Inc.

Inventor： Bruce A. Liikanen ,  Michael Sheperek

IPC: G06F11/10 ,  G06F3/06

Abstract: The present disclosure is directed to logic based read sample offset operations in a memory sub-system. A processing device performs a first read, a second read, and a third read of data from a memory devices using a first center value corresponding to a first read level threshold, a negative offset value, and a positive offset value, respectively. The processing device performs a XOR operation on results from the first and second reads to obtain a first value and a XOR operation on results from the second and third reads to obtain a second value. The processing device performs a first count operation on the first value to determine a first difference bit count and a second count operation on the second value to determine a second difference bit count. The processing device can store or output the first difference bit count and the second difference bit count.

公开(公告)号：US11069416B2

公开(公告)日：2021-07-20

申请号：US16848267

申请日：2020-04-14

Applicant: Micron Technology, Inc.

Inventor： Michael Sheperek ,  Larry J. Koudele ,  Bruce A. Liikanen

IPC: G11C16/06 ,  G11C16/34 ,  G11C16/10 ,  G11C11/56

Abstract: Described herein are embodiments related to first-pass dynamic program targeting (DPT) operations on memory cells of memory systems. A processing device determines that a first programming pass of a programming operation has been performed on a memory cell of a memory component. The processing device, before a second programming pass of the programming operation is performed on the memory cell, determines information about a first programming distribution and a second programming distribution of the memory cell, the first programming distribution corresponding to a first page type and the second programming distribution corresponding to a second page type. The processing device adjusts, using the information, a placement of the first programming distribution relative to the second programming distribution that balances a bit error rate (BER) between the first page type and the second page type.

公开(公告)号：US20210181993A1

公开(公告)日：2021-06-17

申请号：US17187266

申请日：2021-02-26

Applicant: Micron Technology, Inc.

Inventor： Gerald L. Cadloni ,  Michael Sheperek ,  Francis Chew ,  Bruce A. Liikanen ,  Larry J. Koudele

IPC: G06F3/06 ,  G06F11/10 ,  G11C29/52 ,  G06F13/42 ,  G06F13/16

Abstract: Aspects of the present disclosure are directed to performing varying frequency memory sub-system background scans using either or both a timer and an I/O event limit. This can be accomplished by identifying a background scan trigger event from one of multiple possible types of background scan trigger events, such as a timer expiration or reaching an event count limit. In response to the background scan trigger event, a background scan can be initiated on a memory portion. The background scan can produce results, such as CDF-based data. When a metric based on the results exceeds a background scan limit, a refresh relocation can be performed and logged. A metric can be generated based on the CDF-based data, obtained error recovery depth data, or refresh relocation event data. When the metric is above or below corresponding background scan thresholds, a background scan frequency can be adjusted.

公开(公告)号：US11003383B2

公开(公告)日：2021-05-11

申请号：US16514588

申请日：2019-07-17

Applicant: Micron Technology, Inc.

Inventor： Michael Sheperek ,  Larry J. Koudele ,  Bruce A. Liikanen

IPC: G11C16/26 ,  G06F3/06

Abstract: A data structure is generated that identifies a shape of a valley that is located between programming distributions of the memory component. The data structure identifies read level thresholds at the valley associated with a logical page type of the memory component. For each of the read level thresholds the data structure associates a respective error count. A read level threshold is estimated using the data structure. A read operation is performed at the memory component using the read level threshold identified using the data structure.

公开(公告)号：US10936246B2

公开(公告)日：2021-03-02

申请号：US16156904

申请日：2018-10-10

Applicant: Micron Technology, Inc.

Inventor： Gerald L. Cadloni ,  Michael Sheperek ,  Francis Chew ,  Bruce A. Liikanen ,  Larry J. Koudele

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F3/06 ,  G06F11/10 ,  G11C29/52 ,  G06F13/42 ,  G06F13/16 ,  G06F12/02

Abstract: Aspects of the present disclosure are directed to performing varying frequency memory sub-system background scans using either or both a timer and an I/O event limit. This can be accomplished by identifying a background scan trigger event from one of multiple possible types of background scan trigger events, such as a timer expiration or reaching an event count limit. In response to the background scan trigger event, a background scan can be initiated on a memory portion. The background scan can produce results, such as CDF-based data. When a metric based on the results exceeds a background scan limit, a refresh relocation can be performed and logged. A metric can be generated based on the CDF-based data, obtained error recovery depth data, or refresh relocation event data. When the metric is above or below corresponding background scan thresholds, a background scan frequency can be adjusted.

公开(公告)号：US20210019208A1

公开(公告)日：2021-01-21

申请号：US16514644

申请日：2019-07-17

Applicant: Micron Technology, Inc.

Inventor： Michael Sheperek ,  Larry J. Koudele ,  Bruce A. Liikanen

IPC: G06F11/07 ,  G11C16/10 ,  G11C16/28 ,  G11C16/08

Abstract: Center error counts are determined for logical page types of the memory component. A first center error count is indicative of a number of bit errors for a first logical page type. A second center error count is indicative of a number of bit errors for a second logical page type. A modified page margin is determined based on a current page margin corresponding to the first logical page type. The current page margin corresponds to the first logical page type and is indicative of a ratio of the first center error count to the second center error count. The modified page margin is indicative of a modified ratio of a modified first center error count to the second center error count. The current page margin is adjusted corresponding to the first logical page type in accordance with the modified page margin.

公开(公告)号：US20210019078A1

公开(公告)日：2021-01-21

申请号：US16514588

申请日：2019-07-17

Applicant: Micron Technology, Inc.

Inventor： Michael Sheperek ,  Larry J. Koudele ,  Bruce A. Liikanen

IPC: G06F3/06

Abstract: A data structure is generated that identifies a shape of a valley that is located between programming distributions of the memory component. The data structure identifies read level thresholds at the valley associated with a logical page type of the memory component. For each of the read level thresholds the data structure associates a respective error count. A read level threshold is estimated using the data structure. A read operation is performed at the memory component using the read level threshold identified using the data structure.

公开(公告)号：US12040026B2

公开(公告)日：2024-07-16

申请号：US17506587

申请日：2021-10-20

Applicant: Micron Technology, Inc.

Inventor： Bruce A. Liikanen ,  Larry J. Koudele ,  Michael Sheperek

IPC: G11C16/34 ,  G11C5/04 ,  G11C11/56

CPC classification number: G11C16/3404 ,  G11C5/04 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/3459 ,  G11C2211/5623 ,  G11C2211/5624 ,  G11C2211/5625

Abstract: A processing device determines difference error counts that are indicative of relative widths of valleys. Each of the valleys is located between a respective pair of programming distributions of memory cells of the memory device. A program targeting operation is performed on a memory cell of the memory device to calibrate one or more program verify (PV) targets associated with the programming distributions. To perform the program targeting operation, a rule from a set of rules is selected based on the difference error counts. The set of rules corresponds to an adjusting of a PV target of a last programming distribution. One or more program verify (PV) targets associated with the programming distributions are adjusted based on the selected rule.