公开(公告)号：US06750683B2

公开(公告)日：2004-06-15

申请号：US09846524

申请日：2001-04-30

申请人： David C. McClure ,  Rong Yin

发明人： David C. McClure ,  Rong Yin

IPC分类号： H03K522

CPC分类号： G01R19/16547

摘要： A circuit and method are disclosed for monitoring the voltage level of an unregulated power supply. The circuit includes a voltage reference circuit for generating a first reference voltage signal and a trim circuit which generates a trimmed reference voltage signal based upon the first reference voltage signal. A comparator compares the unregulated power supply voltage to the trimmed reference voltage signal and asserts an output signal based upon the comparison. The output signal is fed back as an input to the trim circuit so that the trim circuit provides a hysteresis effect.

摘要翻译： 公开了一种用于监测未调节电源的电压电平的电路和方法。 电路包括用于产生第一参考电压信号的电压参考电路和基于第一参考电压信号产生修整的参考电压信号的微调电路。 比较器将未调节的电源电压与修整的参考电压信号进行比较，并根据比较确定输出信号。 输出信号作为输入反馈到微调电路，使得微调电路提供滞后效应。

公开(公告)号：US06476669B2

公开(公告)日：2002-11-05

申请号：US09902206

申请日：2001-07-10

申请人： David C. McClure ,  Rong Yin

发明人： David C. McClure ,  Rong Yin

IPC分类号： H03K1772

CPC分类号： G05F3/242

摘要： A reference voltage trim circuit includes a voltage follower receiving the reference voltage to be trimmed, with one or more resistive loads providing predefined voltage shifts serially connected between the output of the voltage follower and the output of the trim circuit. The voltage follower includes a current mirror differential amplifier receiving the reference voltage at one input and the output of the voltage follower at the other input, and a transistor with a resistive load connected between the power supply voltages and receiving the output of the current mirror differential amplifier at the transistor's gate. The resistive loads provide varying preselected voltage drop and are each shunted by corresponding fuses, with the entire series of resistive loads shunted by a master fuse. To trim the reference voltage, at least the master fuse is blown, together with the fuse(s) shunting resistive loads which combine to result in the desired trim voltage. Pass gates control which end of the resistive load series is connected to the output of the voltage follower and which is connected to the output of the trim circuit. To decrement the reference voltage, a first end is connected to the output of the voltage follower and the second end is connected to trim circuit output; to increment the reference voltage, the second end of the resistive load series is connected to the voltage follower output and the first end is connected to the trim circuit output.

摘要翻译： 参考电压调整电路包括接收要修整的参考电压的电压跟随器，其中一个或多个电阻负载提供串联连接在电压跟随器的输出端和微调电路的输出之间的预定电压偏移。 电压跟随器包括电流反射镜差分放大器，其在一个输入处接收参考电压，并在另一个输入端接收电压跟随器的输出;以及晶体管，其电阻负载连接在电源电压之间并接收电流镜差分的输出 放大器在晶体管的门。 电阻负载提供变化的预选电压降，并且每个分压由对应的保险丝分流，整个电阻负载系列由主保险丝分流。 为了修整参考电压，至少主保险丝与熔断器一起分流电阻性负载，结合起来产生所需的调整电压。 通路控制电阻负载系列的哪一端连接到电压跟随器的输出端并连接到微调电路的输出。 为了减小参考电压，第一端连接到电压跟随器的输出端，第二端连接到微调电路输出; 为了增加参考电压，电阻负载系列的第二端连接到电压跟随器输出，第一端连接到微调电路输出。

公开(公告)号：US6037799A

公开(公告)日：2000-03-14

申请号：US758587

申请日：1996-11-27

申请人： David C. McClure

发明人： David C. McClure

IPC分类号： G11C11/413 ,  G11C29/00 ,  G11C29/04 ,  G11C29/24 ,  H03K19/173

CPC分类号： G11C29/24 ,  G11C29/785 ,  G11C29/80 ,  G11C29/808 ,  G11C29/84

摘要： A multiplexing circuit includes a reference terminal, a plurality of multiplexing input terminals, and a buffer having an input terminal and an output terminal. The multiplexing circuit also includes a plurality of first elements that each have a programmable conductivity and that are each serially coupled between a corresponding one of the multiplexing input terminals and the input terminal of the buffer. When one of the input signals is to be coupled to the multiplexer output terminal, the element corresponding to the selected input signal is programmed in a conductive state, and the remaining elements are programmed in a nonconductive state. When none of the input signals are selected, each element is programmed in a conductive state and the input signals each have the same value so as to prevent signal conflicts and short circuits at nodes within the multiplexing circuit.

摘要翻译： 复用电路包括参考终端，多个复用输入端和具有输入端和输出端的缓冲器。 多路复用电路还包括多个第一元件，每个第一元件具有可编程导电性并且各自串联耦合在相应的多路复用输入端子和缓冲器的输入端之间。 当输入信号中的一个要被耦合到多路复用器输出端时，对应于所选择的输入信号的元件被编程为导通状态，并且其余元件被编程为非导通状态。 当没有选择输入信号时，每个元件被编程为导通状态，并且输入信号各自具有相同的值，以便防止复用电路内的节点处的信号冲突和短路。

公开(公告)号：US5896336A

公开(公告)日：1999-04-20

申请号：US974747

申请日：1997-11-19

申请人： David C. McClure

发明人： David C. McClure

IPC分类号： G11C7/06 ,  G11C7/10 ,  G11C7/12 ,  G11C11/419 ,  G11C7/00

CPC分类号： G11C7/1057 ,  G11C11/419 ,  G11C7/06 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/12

摘要： A signal driver receives an input signal and an enable signal, and generates an output signal from the input signal when the enable signal has an active state. When the enable signal has an inactive state, the signal driver draws substantially zero supply current regardless of the level of the input signal. The enable signal may be the sense-amplifier enable signal. The signal driver may also include an input circuit that receives the input signal and generates an intermediate signal from the input signal when the enable signal has the first state. An output circuit is coupled to the input circuit, receives the intermediate signal, and generates the output signal from the intermediate signal. A switch circuit is coupled to the input circuit, receives the enable signal, and cuts off substantially all supply current to the input circuit when the enable signal has the second state.

摘要翻译： 信号驱动器接收输入信号和使能信号，并且当使能信号具有活动状态时，从输入信号产生输出信号。 当使能信号具有无效状态时，无论输入信号的电平如何，信号驱动器都基本上绘制零电源电流。 使能信号可以是读出放大器使能信号。 当使能信号具有第一状态时，信号驱动器还可以包括接收输入信号并从输入信号产生中间信号的输入电路。 输出电路耦合到输入电路，接收中间信号，并从中间信号产生输出信号。 当使能信号具有第二状态时，开关电路耦合到输入电路，接收使能信号，并且切断基本上所有输入到输入电路的电流。

公开(公告)号：US5883838A

公开(公告)日：1999-03-16

申请号：US929987

申请日：1997-09-15

申请人： David C. McClure

发明人： David C. McClure

IPC分类号： G11C7/06 ,  G11C7/10 ,  G11C7/12 ,  G11C11/419 ,  G11C7/00

CPC分类号： G11C7/1057 ,  G11C11/419 ,  G11C7/06 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/12

摘要： A signal driver receives an input signal and an enable signal, and generates an output signal from the input signal when the enable signal has an active state. When the enable signal has an inactive state, the signal driver draws substantially zero supply current regardless of the level of the input signal. The enable signal may be the sense-amplifier enable signal. The signal driver may also include an input circuit that receives the input signal and generates an intermediate signal from the input signal when the enable signal has the first state. An output circuit is coupled to the input circuit, receives the intermediate signal, and generates the output signal from the intermediate signal. A switch circuit is coupled to the input circuit, receives the enable signal, and cuts off substantially all supply current to the input circuit when the enable signal has the second state.

公开(公告)号：US5861660A

公开(公告)日：1999-01-19

申请号：US710356

申请日：1996-09-17

申请人： David C. McClure

发明人： David C. McClure

IPC分类号： G01R31/28 ,  G01R31/30 ,  G01R31/3185 ,  G06F11/22 ,  G11C29/00 ,  G11C29/26 ,  G11C29/56 ,  H01L23/58 ,  H01L23/544

CPC分类号： H01L22/32 ,  G01R31/30 ,  G01R31/318505 ,  G01R31/318511 ,  G11C29/26 ,  G06F11/2273 ,  H01L2924/0002 ,  H01L2924/3011

摘要： A semiconductor integrated-circuit die includes a substrate of semiconductor material that has an edge. A conductive layer is disposed on the substrate, and a first insulator layer is disposed between the said substrate and the conductive layer. A functional circuit is disposed in the die. A conductive path is disposed beneath the insulator layer and is coupled to the circuit, the conductive path having an end portion that is located substantially at the edge of the substrate. The wafer on which the die is disposed has one or more signal lines that run along the scribe lines of the wafer. Before the die is scribed from the wafer, the conductive path couples the circuit on the die to one of these signal lines. The end portion of the conductive path is formed when the die is scribed from the wafer.

摘要翻译： 半导体集成电路管芯包括具有边缘的半导体材料的衬底。 导电层设置在基板上，第一绝缘层设置在所述基板和导电层之间。 功能电路设置在模具中。 导电路径设置在绝缘体层下方并且耦合到电路，导电路径具有基本位于衬底边缘处的端部。 其上设置管芯的晶片具有沿着晶片的划线延伸的一条或多条信号线。 在从晶片划线之前，导电路径将管芯上的电路耦合到这些信号线之一。 导电路径的端部在晶片被刻划时形成。

公开(公告)号：US5841709A

公开(公告)日：1998-11-24

申请号：US758586

申请日：1996-11-27

申请人： David C. McClure

发明人： David C. McClure

IPC分类号： G11C11/413 ,  G11C29/00 ,  G11C29/04 ,  G11C29/24

CPC分类号： G11C29/24 ,  G11C29/785 ,  G11C29/80 ,  G11C29/808 ,  G11C29/84

摘要： A memory device includes an array of matrix memory cells that each correspond to a matrix location within the matrix array, an array of redundant memory cells that each correspond to a redundant location within the redundant array, and address and test circuitry. During a first test mode that is performed before any redundant cells have been mapped to the addresses of matrix locations, the address and test circuitry simultaneously addresses all of the matrix locations and selects all of the redundant memory cells. During a second test mode that is performed after the first test mode, the address and test circuitry simultaneously addresses all of the matrix locations and selects only those redundant memory cells that are mapped to the addresses of matrix locations. Typically, the redundant memory cells are so mapped to replace defective matrix memory cells.

摘要翻译： 存储器件包括矩阵存储器单元阵列，每个矩阵存储器单元阵列对应于矩阵阵列内的矩阵位置，每个对应于冗余阵列内的冗余位置的冗余存储器单元阵列以及地址和测试电路。 在将任何冗余单元映射到矩阵位置的地址之前执行的第一测试模式期间，地址和测试电路同时寻址所有矩阵位置并选择所有冗余存储单元。 在第一测试模式之后执行的第二测试模式期间，地址和测试电路同时寻址所有矩阵位置，并且仅选择映射到矩阵位置的地址的那些冗余存储器单元。 通常，冗余存储器单元被如此映射以代替有缺陷的矩阵存储单元。

公开(公告)号：US5768206A

公开(公告)日：1998-06-16

申请号：US484491

申请日：1995-06-07

申请人： David C. McClure

发明人： David C. McClure

IPC分类号： G11C7/12 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00

CPC分类号： G11C29/785 ,  G11C29/80 ,  G11C29/832 ,  G11C7/12

摘要： A circuit biases an associated pair of bit lines. A fuse is coupled between a biasing voltage and a node. A first load is coupled between the node and a first of the bit lines. A second load is coupled between the node and a second of the bit lines.

摘要翻译： 电路偏置相关的一对位线。 熔断器耦合在偏置电压和节点之间。 第一负载耦合在节点与第一位线之间。 第二负载耦合在节点和第二位线之间。

公开(公告)号：US5745432A

公开(公告)日：1998-04-28

申请号：US589141

申请日：1996-01-19

申请人： David C. McClure

发明人： David C. McClure

IPC分类号： G11C7/10 ,  G11C8/00 ,  G11C7/00

CPC分类号： G11C7/1078

摘要： A driver circuit writes data to a memory cell during a write cycle and uncouples the write power terminals from the write terminals during a test mode. The driver circuit includes a first and second data input terminals that typically receive complementary data signals during a write cycle, a test terminal, a write-enable terminal, first and second write power terminals, and first and second write terminals that are coupled to the memory cell. The circuit respectively uncouples the first and second write terminals from the first and second write power terminals when a first signal level, which indicates the test mode, is present on the test terminal. The driver circuit may also couple the first and second write terminals to a reference voltage such as a ground voltage when the first signal level is present on the test terminal.

摘要翻译： 驱动电路在写周期期间将数据写入存储单元，并在测试模式期间将写入电源端与写入端分离。 驱动器电路包括在写周期期间通常接收互补数据信号的第一和第二数据输入端，测试终端，写使能端，第一和第二写功率端以及耦合到 记忆单元 当在测试终端上存在指示测试模式的第一信号电平时，该电路分别将第一和第二写入端子与第一和第二写入电源端子断开。 当测试终端上存在第一信号电平时，驱动电路还可以将第一和第二写入端子耦合到参考电压，例如接地电压。

公开(公告)号：US5691950A

公开(公告)日：1997-11-25

申请号：US588740

申请日：1996-01-19

申请人： David C. McClure

发明人： David C. McClure

IPC分类号： G11C11/413 ,  G11C7/10 ,  G11C11/401 ,  G11C11/41 ,  G11C7/00

CPC分类号： G11C7/10 ,  G11C7/1006

摘要： A memory device includes an address decoder, a global data line, and a plurality of memory blocks, which are each coupled to the address decoder and the global data line. Each memory block includes a plurality of column lines, a local data line, and a plurality of memory cells that are arranged in columns and are each coupled to a corresponding one of the column lines. Each memory block also includes or has associated therewith a switching circuit that is coupled to the column lines and the local data line. The switching circuit couples a selected column line to the local data line and couples the local data line to the global data line when the memory block is selected. The switching circuit uncouples each of the column lines from the local data line when the memory block is unselected, or during a read cycle when the memory block is selected and the sense-amplifier is enabled.

摘要翻译： 存储器件包括地址解码器，全局数据线和多个存储器块，它们分别耦合到地址解码器和全局数据线。 每个存储器块包括多个列线，本地数据线和多个存储器单元，其被布置成列并且各自耦合到相应的列线之一。 每个存储器块还包括或者与其相关联的一个切换电路，其连接到列线和本地数据线。 当选择存储块时，开关电路将选定的列线耦合到本地数据线并将本地数据线耦合到全局数据线。 当存储器块未选择时，或者在选择存储器块并且使能了读出放大器的读取周期期间，开关电路将每条列线与本地数据线断开。