公开(公告)号：US07918549B2

公开(公告)日：2011-04-05

申请号：US11757051

申请日：2007-06-01

申请人： Kazuhiko Amano ,  Naoyuki Toyoda ,  Hiroyuki Hara ,  Takayuki Kondo

发明人： Kazuhiko Amano ,  Naoyuki Toyoda ,  Hiroyuki Hara ,  Takayuki Kondo

IPC分类号： B41J2/175

CPC分类号： B41J2/17546 ,  B41J2/1752 ,  B41J2/1753 ,  B41J2/17553 ,  B41J2/17566

摘要： An ink cartridge filled with an ink added with an infrared absorption material with a function of absorbing an infrared ray to distinguish the ink from another ink of a same color, the ink cartridge used in a loaded state where the ink cartridge is loaded into a printing apparatus for performing printing, the ink cartridge includes an ink supplying system including a storage portion for storing the ink, an outlet for supplying the ink to the printing apparatus in the loaded state, and a flow path for guiding the ink from the storage portion to the outlet, a light emitter, a sensor including a light receiver disposed in opposition to the light emitter with the ink supplying system intervened therebetween, the light receiver for receiving transmitted light resulting from transmission of emitted light from the light emitter through the ink supplying system, and an ink cartridge-side terminal electrically connected to the sensor, coming in contact with an apparatus-side terminal provided to the printing apparatus in the loaded state, in which the emitted light has a wavelength in an infrared range.

摘要翻译： 一种填充有添加有红外线吸收材料的墨水的墨盒，其具有吸收红外线的功能，以将墨水与另一种相同颜色的墨水区分开，墨盒用于将墨盒装入打印机的加载状态 用于执行打印的设备，墨盒包括一个供墨系统，该供墨系统包括一个用于储存墨水的储存部分，一个用于在装载状态下将墨水供给打印装置的出口，以及用于将油墨从储存部分引导到 所述出口，发光器，包括与所述光发射器相对设置的光接收器的传感器，所述光接收器插入在所述供墨系统之间，所述光接收器用于接收从所述发光器通过所述供墨系统发射的发射光所产生的透射光 以及电连接到传感器的墨盒侧端子，与设置侧端子t相接触 o处于负载状态的打印装置，其中发射的光具有红外范围的波长。

公开(公告)号：US07911639B2

公开(公告)日：2011-03-22

申请号：US11801552

申请日：2007-05-10

申请人： Hiroyuki Hara

发明人： Hiroyuki Hara

IPC分类号： G06K15/00 ,  G06F3/12

CPC分类号： G06F9/5016 ,  G06F9/544 ,  G06F12/109

摘要： A method that enables an image forming device of efficient memory sharing between processes and a kernel in a simple multiple-process-configuration. The image forming device has a real address space including a DMA buffer area and a shared memory area, a virtual address spaces, and job page assurance (JPA) programs. The virtual address spaces of the executing processes are mapped onto the real address space. The DMA buffer area can be accessed by the kernel. The shared memory area stores a job list and a job management list. The processes in the virtual address spaces include identical JPA libraries. Each of the JPA libraries requests the kernel to allocate of one page non-compressed data memory size for the job in the DMA buffer area, and upon completion of the job output, requests the kernel to release the allocated area and alters the contents in the job management list accordingly.

摘要翻译： 一种能够在简单的多进程配置中使得能够在进程和内核之间共享有效的内存的图像形成装置的方法。 图像形成装置具有包括DMA缓冲区域和共享存储区域，虚拟地址空间和作业页面保证（JPA）程序的实际地址空间。 执行进程的虚拟地址空间映射到实际地址空间。 内存可以访问DMA缓冲区。 共享内存区存储作业列表和作业管理列表。 虚拟地址空间中的进程包括相同的JPA库。 每个JPA库请求内核为DMA缓冲区中的作业分配一页非压缩数据存储器大小，并且在完成作业输出后，请求内核释放分配的区域并更改内容 相应的工作管理清单。

公开(公告)号：US20100315127A1

公开(公告)日：2010-12-16

申请号：US12701730

申请日：2010-02-08

申请人： Chenkong Teh ,  Hiroyuki Hara

发明人： Chenkong Teh ,  Hiroyuki Hara

IPC分类号： H03K19/094 ,  H03K19/20

CPC分类号： H03K3/356191

摘要： A semiconductor integrated circuit device includes: a first inverter constituted by a first transistor configured to charge a charge point based on an input signal, and a second transistor configured to discharge a discharge point based on the input signal; a P-type third transistor and an N-type fourth transistor with drain-source paths provided in parallel between the charge point and the discharge point; and a second inverter configured to invert a potential of the charge point or the discharge point and supply the inverted potential to gates of the third and fourth transistors, and obtain a delay signal of the input signal from the charge point or the discharge point. The semiconductor integrated circuit device secures a sufficient delay time with a small area.

摘要翻译： 一种半导体集成电路器件，包括：由基于输入信号对充电点充电的第一晶体管构成的第一反相器和基于输入信号对放电点进行放电的第二晶体管; P型第三晶体管和N型第四晶体管，其漏极源路径并联设置在充电点和放电点之间; 以及第二反相器，被配置为反转充电点或放电点的电位，并将反相电势提供给第三和第四晶体管的栅极，并从充电点或放电点获得输入信号的延迟信号。 半导体集成电路器件以小的面积确保足够的延迟时间。

公开(公告)号：US07487370B2

公开(公告)日：2009-02-03

申请号：US11216018

申请日：2005-09-01

申请人： Shinichiro Shiratake ,  Yukihito Oowaki ,  Hiroyuki Hara ,  Tetsuya Fujita ,  Fumitoshi Hatori ,  Masataka Matsui

发明人： Shinichiro Shiratake ,  Yukihito Oowaki ,  Hiroyuki Hara ,  Tetsuya Fujita ,  Fumitoshi Hatori ,  Masataka Matsui

IPC分类号： G06F1/00

CPC分类号： G06F1/26 ,  G06F1/3203 ,  G06F1/3296 ,  Y02D10/172

摘要： According to the present invention, there is provided a semiconductor device including a power supply circuit which receives an external power supply voltage supplied, and outputs an internal power supply voltage not higher than the external power supply voltage; a system module which receives the internal power supply voltage, and performs a predetermined operation; and a performance monitor circuit which measures a processing speed of said system module when the internal power supply voltage is applied, and, on the basis of the processing speed, outputs a first control signal which requests to set the external power supply voltage at a first level, and a second control signal which requests said power supply circuit to set the internal power supply voltage at a second level. The power supply circuit outputs the internal power supply voltage having the second level on the basis of the second control signal applied thereto.

摘要翻译： 根据本发明，提供了一种半导体器件，包括：电源电路，接收所提供的外部电源电压，并输出不高于外部电源电压的内部电源电压; 接收内部电源电压并执行预定操作的系统模块; 以及性能监视电路，其在施加所述内部电源电压时测量所述系统模块的处理速度，并且基于所述处理速度，输出请求将所述外部电源电压设置为第一的第一控制信号 电平和第二控制信号，其请求所述电源电路将内部电源电压设定在第二电平。 电源电路基于施加到其上的第二控制信号输出具有第二电平的内部电源电压。

公开(公告)号：US07486809B2

公开(公告)日：2009-02-03

申请号：US11041265

申请日：2005-01-25

申请人： Hiroyuki Hara ,  Mitsutoshi Miyasaka

发明人： Hiroyuki Hara ,  Mitsutoshi Miyasaka

IPC分类号： G06K9/00

CPC分类号： G06K9/0002 ,  G01D5/2405

摘要： Aspects of the invention can provide a fingerprint sensor for searching for a detection condition in a short period of time in order to read information of ridges and valleys of a fingerprint as changes in capacitance. The fingerprint sensor of the invention can include a plurality of capacitance detection circuits that output a detection signal having ridge/valley information of a fingerprint based on capacitance formed between the sensor and a fingertip surface, a fingerprint detection part in which the plurality of capacitance detection circuits are arranged to intersect with one another in a row direction and a column direction, a plurality of scanning lines, a scanning line driver for driving the scanning line, a plurality of data lines, a data line driver for driving the data line, and search device for searching for a detection condition of ridge/valley information by changing detection conditions of the ridge/valley information in a state that the plurality of capacitance detection circuits arranged along any one of the plurality of scanning lines are being selected.

摘要翻译： 本发明的方面可以提供一种用于在短时间内搜索检测条件的指纹传感器，以便读取指纹的脊和谷的信息作为电容的变化。 本发明的指纹传感器可以包括多个电容检测电路，其输出具有基于在传感器和指尖表面之间形成的电容的指纹的脊/谷信息的检测信号，指纹检测部分中的多个电容检测 电路被布置为在行方向和列方向上彼此相交，多条扫描线，用于驱动扫描线的扫描线驱动器，多条数据线，用于驱动数据线的数据线驱动器，以及 搜索装置，用于通过在选择沿着多条扫描线中的任何一条布置的多个电容检测电路的状态下改变脊谷信息的检测条件来搜索脊谷信息的检测条件。

公开(公告)号：US20080291496A1

公开(公告)日：2008-11-27

申请号：US12124538

申请日：2008-05-21

申请人： Hiroyuki Hara

发明人： Hiroyuki Hara

IPC分类号： G06F3/12

CPC分类号： G06K15/181 ,  G06F3/1297 ,  G06K15/00 ,  G06K15/02 ,  G06K15/1827 ,  G06K15/1851 ,  G06K15/1857 ,  G06K15/1863 ,  H04N2201/0082

摘要： A CPU perform the steps of:(a) causing a compression/decompression processor to decompress the compressed data of one of three bands in the data area except for the first block in the band, and storing decompressed bitmap data in the data area;(b) rasterizing each of the intermediate data blocks in the band and synthesizing the rasterized data and the decompressed bitmap data in the band; and(c) causing the compression/decompression processor to compress the synthesized bitmap data and storing the compressed data in the data area.The CPU performs the steps (a) to (c) in different respective tasks in parallel, and performs the steps (a) to (c) along the order of (a), (b), (c) for each of the intermediate code blocks in each of the bands while using the 1st to the 3rd bitmap data area in turn for each of the steps (a) to (c).

摘要翻译： CPU执行以下步骤：（a）使压缩/解压缩处理器解压缩除频带中的第一块以外的数据区域中的三个频带之一的压缩数据，并将解压缩的位图数据存储在数据区域中; （b）对频带中的每个中间数据块进行光栅化，并合成光栅化数据和频带中的解压缩位图数据; 和（c）使压缩/解压缩处理器压缩合成位图数据并将压缩数据存储在数据区中。 CPU在不同的各个任务中并行执行步骤（a）至（c），并且按照（a），（b），（c）的顺序对于每个中间体执行步骤（a）至（c） 对于每个步骤（a）至（c）中的每一个依次使用第一至第三位图数据区域，每个频带中的代码块。

公开(公告)号：US07352227B2

公开(公告)日：2008-04-01

申请号：US11271848

申请日：2005-11-14

申请人： Shinichiro Shiratake ,  Hiroyuki Hara

发明人： Shinichiro Shiratake ,  Hiroyuki Hara

IPC分类号： H03L5/00

CPC分类号： H03K3/356113

摘要： A first inverter circuit comprises a first transistor in which one end of a current path is grounded, and a second transistor in which one end of a current path is connected to the other end of the current path of the first transistor. A first signal is supplied to gates of the first and second transistors. A third transistor is connected between the other end of the current path of the second transistor and a node to which a second voltage higher than the first voltage is supplied. A control signal constituted of one of the ground potential and the second voltage is supplied to a gate of the third transistor behind a change of a first signal. A second signal constituted of one of the ground potential and the second voltage is output from an output terminal of the first inverter circuit.

摘要翻译： 第一逆变器电路包括其中电流路径的一端接地的第一晶体管和电流路径的一端连接到第一晶体管的电流通路的另一端的第二晶体管。 向第一和第二晶体管的栅极提供第一信号。 第三晶体管连接在第二晶体管的电流通路的另一端和高于第一电压的第二电压的节点之间。 由地电位和第二电压之一组成的控制信号在第一信号的改变之后提供给第三晶体管的栅极。 从第一反相器电路的输出端子输出由接地电位和第二电压之一构成的第二信号。

公开(公告)号：US07245177B2

公开(公告)日：2007-07-17

申请号：US10899004

申请日：2004-07-27

申请人： Tetsuya Fujita ,  Motosugu Hamada ,  Hiroyuki Hara

发明人： Tetsuya Fujita ,  Motosugu Hamada ,  Hiroyuki Hara

IPC分类号： G05F3/24

CPC分类号： G05F3/205

摘要： This disclosure concerns semiconductor integrated circuit includes a semiconductor substrate; a plurality of well regions formed on one surface of the semiconductor substrate and electrically isolated from each other; a plurality of MOS transistors formed in the well regions; and a substrate bias generator applying substrate biases to the individual well regions based on actually measured process-derived variance of the MOS transistors in threshold voltage to bring the threshold voltages of the respective MOS transistors into conformity with a normal threshold voltage.

摘要翻译： 本公开涉及半导体集成电路包括半导体衬底; 多个阱区，形成在所述半导体衬底的一个表面上并彼此电隔离; 形成在所述阱区中的多个MOS晶体管; 以及衬底偏置发生器，其基于实际测量的阈值电压下的MOS晶体管的工艺导出方差，将衬底偏压到各个阱区域，以使各个MOS晶体管的阈值电压与正常阈值电压一致。

公开(公告)号：US20070115314A1

公开(公告)日：2007-05-24

申请号：US11465065

申请日：2006-08-16

申请人： Takayuki Kondo ,  Hiroyuki Hara ,  Naoyuki Toyoda ,  Kazuhiko Amano

发明人： Takayuki Kondo ,  Hiroyuki Hara ,  Naoyuki Toyoda ,  Kazuhiko Amano

IPC分类号： B41J29/393

CPC分类号： B41J2/17566 ,  B41J2002/17573 ,  G01N21/3504 ,  H01L24/83 ,  H01L2224/83001 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/14 ,  H01L2924/00

摘要： An optical sensor for identifying a subject includes a light absorption member with light absorption characteristics adjusted independently from the subject so that the optical sensor identifies the subject by optically identifying the light absorption member, a light emitting device for radiating reference light having a peak wavelength in an absorption wavelength region of the light absorption member to the subject, a light receiving device for receiving the reference light transmitted through the subject, and an integrated circuit board provided with the light emitting device and the light receiving device on a substrate face.

摘要翻译： 用于识别对象的光学传感器包括具有独立于被摄体调节的光吸收特性的光吸收构件，以使得光学传感器通过光学识别光吸收构件来识别被摄体，发光装置，用于辐射具有峰值波长的参考光 光吸收构件对受试者的吸收波长区域，用于接收通过被检体透射的参考光的光接收装置，以及在基板面上设置有发光装置和受光装置的集成电路基板。

公开(公告)号：US07072866B1

公开(公告)日：2006-07-04

申请号：US09648870

申请日：2000-08-25

申请人： Hiroyuki Hara

发明人： Hiroyuki Hara

IPC分类号： G06F17/00

CPC分类号： G03G21/02 ,  H04N1/00204 ,  H04N1/34 ,  H04N2201/0081 ,  H04N2201/0082 ,  H04N2201/0091 ,  H04N2201/0093

摘要： The charge for application software used to input/output data is calculated independently of the charge for a device used to input/output the data, thereby flexibly charging for data input/output.

摘要翻译： 用于输入/输出数据的应用软件的费用与用于输入/输出数据的设备的费用无关，从而灵活地为数据输入/输出充电。