公开(公告)号：US07245177B2

公开(公告)日：2007-07-17

申请号：US10899004

申请日：2004-07-27

申请人： Tetsuya Fujita ,  Motosugu Hamada ,  Hiroyuki Hara

发明人： Tetsuya Fujita ,  Motosugu Hamada ,  Hiroyuki Hara

IPC分类号： G05F3/24

CPC分类号： G05F3/205

摘要： This disclosure concerns semiconductor integrated circuit includes a semiconductor substrate; a plurality of well regions formed on one surface of the semiconductor substrate and electrically isolated from each other; a plurality of MOS transistors formed in the well regions; and a substrate bias generator applying substrate biases to the individual well regions based on actually measured process-derived variance of the MOS transistors in threshold voltage to bring the threshold voltages of the respective MOS transistors into conformity with a normal threshold voltage.

摘要翻译： 本公开涉及半导体集成电路包括半导体衬底; 多个阱区，形成在所述半导体衬底的一个表面上并彼此电隔离; 形成在所述阱区中的多个MOS晶体管; 以及衬底偏置发生器，其基于实际测量的阈值电压下的MOS晶体管的工艺导出方差，将衬底偏压到各个阱区域，以使各个MOS晶体管的阈值电压与正常阈值电压一致。

公开(公告)号：US07551019B2

公开(公告)日：2009-06-23

申请号：US11764605

申请日：2007-06-18

申请人： Tetsuya Fujita ,  Mototsugu Hamada ,  Hiroyuki Hara

发明人： Tetsuya Fujita ,  Mototsugu Hamada ,  Hiroyuki Hara

IPC分类号： G05F3/16 ,  H03L1/00

CPC分类号： G05F3/205

摘要： This disclosure concerns a semiconductor integrated circuit that includes a semiconductor substrate, a plurality of well regions formed on one surface of the semiconductor substrate and electrically isolated from each other, a plurality of MOS transistors formed in the well regions and a substrate bias generator that applies substrate biases to the individual well regions based on actually measured process-derived variance of the MOS transistors in threshold voltage to bring the threshold voltages of the respective MOS transistors into conformity with a normal threshold voltage.

摘要翻译： 本公开涉及一种半导体集成电路，其包括半导体衬底，形成在半导体衬底的一个表面上并彼此电隔离的多个阱区，形成在阱区中的多个MOS晶体管和衬底偏置发生器，其应用 基于实际测量的阈值电压下的MOS晶体管的工艺衍生方差，使各个MOS晶体管的阈值电压与正常阈值电压一致，从而将衬底偏置到各个阱区。

公开(公告)号：US07417489B2

公开(公告)日：2008-08-26

申请号：US11342617

申请日：2006-01-31

申请人： Tetsuya Fujita ,  Fumitoshi Hatori ,  Mototsugu Hamada ,  Hiroyuki Hara ,  Shinichiro Shiratake

发明人： Tetsuya Fujita ,  Fumitoshi Hatori ,  Mototsugu Hamada ,  Hiroyuki Hara ,  Shinichiro Shiratake

IPC分类号： G05F1/10

CPC分类号： G11C5/147

摘要： A semiconductor integrated circuit comprising: a power controller which outputs a voltage select signal for selecting one of at least two types of voltages; a power supply voltage controller which generates and outputs a power supply voltage at an arbitrary voltage change rate on the basis of the voltage select signal; and a circuit portion which receives the power supply voltage and performs processing, wherein said circuit portion keeps operating while said power supply voltage controller is outputting the power supply voltage generated at the arbitrary voltage change rate.

摘要翻译： 一种半导体集成电路，包括：功率控制器，其输出用于选择至少两种类型的电压中的一种的电压选择信号; 电源电压控制器，其基于所述电压选择信号生成并输出任意电压变化率的电源电压; 以及电路部分，其接收电源电压并执行处理，其中所述电路部分在所述电源电压控制器输出以任意电压变化率产生的电源电压的情况下保持操作。

公开(公告)号：US20060271799A1

公开(公告)日：2006-11-30

申请号：US11216018

申请日：2005-09-01

申请人： Shinichiro Shiratake ,  Yukihito Oowaki ,  Hiroyuki Hara ,  Tetsuya Fujita ,  Fumitoshi Hatori ,  Masataka Matsui

发明人： Shinichiro Shiratake ,  Yukihito Oowaki ,  Hiroyuki Hara ,  Tetsuya Fujita ,  Fumitoshi Hatori ,  Masataka Matsui

IPC分类号： G06F1/26

CPC分类号： G06F1/26 ,  G06F1/3203 ,  G06F1/3296 ,  Y02D10/172

摘要： According to the present invention, there is provided a semiconductor device comprising: a power supply circuit which receives an external power supply voltage supplied, and outputs an internal power supply voltage not higher than the external power supply voltage; a system module which receives the internal power supply voltage, and performs a predetermined operation; and a performance monitor circuit which measures a processing speed of said system module when the internal power supply voltage is applied, and, on the basis of the processing speed, outputs a first control signal which requests to set the external power supply voltage at a first level, and a second control signal which requests said power supply circuit to set the internal power supply voltage at a second level, wherein said power supply circuit outputs the internal power supply voltage having the second level on the basis of the second control signal applied thereto.

摘要翻译： 根据本发明，提供了一种半导体器件，包括：电源电路，接收所提供的外部电源电压，并输出不高于外部电源电压的内部电源电压; 接收内部电源电压并执行预定操作的系统模块; 以及性能监视电路，其在施加所述内部电源电压时测量所述系统模块的处理速度，并且基于所述处理速度，输出请求将所述外部电源电压设置为第一的第一控制信号 电平和第二控制信号，其请求所述电源电路将内部电源电压设定在第二电平，其中所述电源电路基于施加到其的第二控制信号输出具有第二电平的内部电源电压 。

公开(公告)号：US20050093611A1

公开(公告)日：2005-05-05

申请号：US10899004

申请日：2004-07-27

申请人： Tetsuya Fujita ,  Mototsugu Hamada ,  Hiroyuki Hara

发明人： Tetsuya Fujita ,  Mototsugu Hamada ,  Hiroyuki Hara

IPC分类号： H01L27/04 ,  G05F3/20 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/092 ,  H03K3/01 ,  H03K17/00

CPC分类号： G05F3/205

摘要： A semiconductor integrated circuit comprises a semiconductor substrate; a plurality of well regions formed on one surface of the semiconductor substrate and electrically isolated from each other; a plurality of MOS transistors formed in the well regions; and a substrate bias generating circuit applying substrate biases to individual said well regions based on actually measured process-derived variance of the MOS transistors in threshold voltage to bring the threshold voltages of the respective MOS transistors into conformity with a normal threshold voltage.

摘要翻译： 半导体集成电路包括半导体衬底; 多个阱区，形成在所述半导体衬底的一个表面上并彼此电隔离; 形成在所述阱区中的多个MOS晶体管; 以及衬底偏置产生电路，其基于实际测量的阈值电压下的MOS晶体管的工艺衍生方差将单独的所述阱区域施加衬底偏置，以使各MOS晶体管的阈值电压与正常阈值电压一致。

公开(公告)号：US20070236276A1

公开(公告)日：2007-10-11

申请号：US11764605

申请日：2007-06-18

申请人： Tetsuya FUJITA ,  Mototsugu Hamada ,  Hiroyuki Hara

发明人： Tetsuya FUJITA ,  Mototsugu Hamada ,  Hiroyuki Hara

IPC分类号： H01L29/94

CPC分类号： G05F3/205

摘要： This disclosure concerns a semiconductor integrated circuit that includes a semiconductor substrate, a plurality of well regions formed on one surface of the semiconductor substrate and electrically isolated from each other, a plurality of MOS transistors formed in the well regions and a substrate bias generator that applies substrate biases to the individual well regions based on actually measured process-derived variance of the MOS transistors in threshold voltage to bring the threshold voltages of the respective MOS transistors into conformity with a normal threshold voltage.

摘要翻译： 本公开涉及一种半导体集成电路，其包括半导体衬底，形成在半导体衬底的一个表面上并彼此电隔离的多个阱区，形成在阱区中的多个MOS晶体管和衬底偏置发生器，其应用 基于实际测量的阈值电压下的MOS晶体管的工艺衍生方差，使各个MOS晶体管的阈值电压与正常阈值电压一致，从而将衬底偏置到各个阱区。

公开(公告)号：US20060198198A1

公开(公告)日：2006-09-07

申请号：US11342617

申请日：2006-01-31

申请人： Tetsuya Fujita ,  Fumitoshi Hatori ,  Mototsugu Hamada ,  Hiroyuki Hara ,  Shinichiro Shiratake

发明人： Tetsuya Fujita ,  Fumitoshi Hatori ,  Mototsugu Hamada ,  Hiroyuki Hara ,  Shinichiro Shiratake

IPC分类号： G11C11/34 ,  G11C16/06

CPC分类号： G11C5/147

摘要： According to the present invention, there is provided a semiconductor integrated circuit comprising: a power controller which outputs a voltage select signal for selecting one of at least two types of voltages; a power supply voltage controller which generates and outputs a power supply voltage at an arbitrary voltage change rate on the basis of the voltage select signal; and a circuit portion which receives the power supply voltage and performs processing, wherein said circuit portion keeps operating while said power supply voltage controller is outputting the power supply voltage generated at the arbitrary voltage change rate.

摘要翻译： 根据本发明，提供了一种半导体集成电路，包括：功率控制器，其输出用于选择至少两种类型的电压中的一种的电压选择信号; 电源电压控制器，其基于所述电压选择信号生成并输出任意电压变化率的电源电压; 以及电路部分，其接收电源电压并执行处理，其中所述电路部分在所述电源电压控制器输出以任意电压变化率产生的电源电压的情况下保持操作。

公开(公告)号：US07487370B2

公开(公告)日：2009-02-03

申请号：US11216018

申请日：2005-09-01

申请人： Shinichiro Shiratake ,  Yukihito Oowaki ,  Hiroyuki Hara ,  Tetsuya Fujita ,  Fumitoshi Hatori ,  Masataka Matsui

发明人： Shinichiro Shiratake ,  Yukihito Oowaki ,  Hiroyuki Hara ,  Tetsuya Fujita ,  Fumitoshi Hatori ,  Masataka Matsui

IPC分类号： G06F1/00

CPC分类号： G06F1/26 ,  G06F1/3203 ,  G06F1/3296 ,  Y02D10/172

摘要： According to the present invention, there is provided a semiconductor device including a power supply circuit which receives an external power supply voltage supplied, and outputs an internal power supply voltage not higher than the external power supply voltage; a system module which receives the internal power supply voltage, and performs a predetermined operation; and a performance monitor circuit which measures a processing speed of said system module when the internal power supply voltage is applied, and, on the basis of the processing speed, outputs a first control signal which requests to set the external power supply voltage at a first level, and a second control signal which requests said power supply circuit to set the internal power supply voltage at a second level. The power supply circuit outputs the internal power supply voltage having the second level on the basis of the second control signal applied thereto.

摘要翻译： 根据本发明，提供了一种半导体器件，包括：电源电路，接收所提供的外部电源电压，并输出不高于外部电源电压的内部电源电压; 接收内部电源电压并执行预定操作的系统模块; 以及性能监视电路，其在施加所述内部电源电压时测量所述系统模块的处理速度，并且基于所述处理速度，输出请求将所述外部电源电压设置为第一的第一控制信号 电平和第二控制信号，其请求所述电源电路将内部电源电压设定在第二电平。 电源电路基于施加到其上的第二控制信号输出具有第二电平的内部电源电压。

公开(公告)号：US08873126B2

公开(公告)日：2014-10-28

申请号：US13550815

申请日：2012-07-17

申请人： Naoki Tomikawa ,  Hiroyuki Hara ,  Tomoki Yokota

发明人： Naoki Tomikawa ,  Hiroyuki Hara ,  Tomoki Yokota

IPC分类号： G02F1/03 ,  G02F1/07 ,  G02F1/29 ,  H01H3/00

CPC分类号： G02F1/03 ,  G02F1/134309 ,  G02F2001/133388 ,  G02F2201/124

摘要： An electrooptic device includes first and second substrates that are disposed opposing each other with an electrooptic material layer therebetween, a sealing material that bonds the first and second substrates, a pixel area, and an ion trap portion between the pixel area and the sealing material. The ion trap portion includes first and second electrodes that are formed in a comb-tooth shape and are disposed so that branch electrodes of the first electrode and branch electrodes of the second electrode are engaged with each other. A direction of the branch electrodes intersects with an orientation direction of the electrooptic material at an interface between the electrooptic material layer and the first substrate.

摘要翻译： 电光装置包括彼此相对设置的第一和第二基板，其间具有电光材料层，在像素区域和密封材料之间结合第一和​​第二基板，像素区域和离子捕获部分的密封材料。 离子捕获部包括形成为梳齿形状的第一电极和第二电极，并且被配置为使得第一电极的分支电极和第二电极的分支电极彼此接合。 分支电极的方向在电光材料层和第一基板之间的界面处与电光材料的取向方向相交。

公开(公告)号：US20140063554A1

公开(公告)日：2014-03-06

申请号：US14076221

申请日：2013-11-10

申请人： Hiroyuki Hara

发明人： Hiroyuki Hara

IPC分类号： G06K15/02

CPC分类号： G06K15/181 ,  G06F3/1297 ,  G06K15/00 ,  G06K15/02 ,  G06K15/1827 ,  G06K15/1851 ,  G06K15/1857 ,  G06K15/1863 ,  H04N2201/0082

摘要： A CPU perform the steps of: (a) causing a compression/decompression processor to decompress the compressed data of one of three bands in the data area except for the first block in the band, and storing decompressed bitmap data in the data area; (b) rasterizing each of the intermediate data blocks in the band and synthesizing the rasterized data and the decompressed bitmap data in the band; and (c) causing the compression/decompression processor to compress the synthesized bitmap data and storing the compressed data in the data area. The CPU performs the steps (a) to (c) in different respective tasks in parallel, and performs the steps (a) to (c) along the order of (a), (b), (c) for each of the intermediate code blocks in each of the bands while using the 1st to the 3rd bitmap data area in turn for each of the steps (a) to (c).

摘要翻译： CPU执行以下步骤：（a）使压缩/解压缩处理器解压缩除频带中的第一块以外的数据区域中的三个频带之一的压缩数据，并将解压缩的位图数据存储在数据区域中; （b）对频带中的每个中间数据块进行光栅化，并合成光栅化数据和频带中的解压缩位图数据; 和（c）使压缩/解压缩处理器压缩合成位图数据并将压缩数据存储在数据区中。 CPU在不同的各个任务中并行执行步骤（a）至（c），并且按照（a），（b），（c）的顺序对于每个中间体执行步骤（a）至（c） 对于每个步骤（a）至（c）中的每一个依次使用第一至第三位图数据区域，每个频带中的代码块。