公开(公告)号：US20220406398A1

公开(公告)日：2022-12-22

申请号：US17349321

申请日：2021-06-16

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Toru Miwa ,  Ken Oowada ,  Gerrit Jan Hemink

IPC: G11C29/00 ,  G11C29/02 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34

Abstract: Apparatuses and techniques are described for programming data in memory cells while concurrently storing backup data. Initial pages of multiple bit per cell data are encoded to obtain at least first and second pages of single bit per cell data. The initial pages of multiple bit per cell data are programmed into a primary set of memory cells, while concurrently the first and second pages of single bit per cell data are programmed into first and second backup sets of memory cells, respectively. In the event of a power loss, the first and second pages of single bit per cell data are read from the first and second backup sets of memory cells, and decoded to recover the initial pages of multiple bit per cell data.

公开(公告)号：US20220383956A1

公开(公告)日：2022-12-01

申请号：US17329617

申请日：2021-05-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Xiang Yang ,  Dengtao Zhao

IPC: G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C16/32 ,  G11C16/24

Abstract: A non-volatile memory system adjusts the speed of a memory operation for a subset of non-volatile memory cells. For example, during a GIDL based erase process, the GIDL generation can be dampened for a subset of memory cells (e.g., for a set of NAND strings, or one or more sub-blocks).

公开(公告)号：US11081197B2

公开(公告)日：2021-08-03

申请号：US17066663

申请日：2020-10-09

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Yu-Chung Lien

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/08 ,  G11C16/26 ,  G11C16/24 ,  G11C11/56

Abstract: A methodology and structure for performing an erase verify in non-volatile memory is described. Both the odd wordlines and the even wordlines are driven to a high voltage level. This can be done simultaneously. The simultaneous charging of both the odd wordlines and the even wordlines, even when the erase verify will occur on only one of the odd or even wordlines reduces RC delay in the charging of the wordlines. After the odd and even wordlines are charged, then one set of wordlines, either the odd or even wordlines, is dropped to the erase verify voltage. The erase sense operation is then performed.

公开(公告)号：US20210233589A1

公开(公告)日：2021-07-29

申请号：US17227820

申请日：2021-04-12

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Aaron Lee ,  Gerrit Jan Hemink ,  Ken Oowada ,  Toru Miwa

IPC: G11C16/10 ,  G11C11/56 ,  G11C16/04 ,  G11C16/34 ,  G11C8/18 ,  G11C8/12

Abstract: Apparatuses, systems, and methods are disclosed for concurrently programming non-volatile storage cells, such as those of an SLC NAND array. The non-volatile storage cells may be arranged into a first block comprising a first string of storage cells that intersects with a first word line at a first storage cell, a second block comprising a second string of storage cells that intersects with a second word line at a second storage cell, a bit line electrically connectable to the first string and the second string, and controller configured to apply a programming pulse, at an elevated voltage, to the first word line and second word line to concurrently program the first and second storage cells.

公开(公告)号：US10910060B1

公开(公告)日：2021-02-02

申请号：US16568986

申请日：2019-09-12

Applicant: SanDisk Technologies LLC

Inventor： Jianzhi Wu ,  Xiang Yang

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/26 ,  G11C16/32

Abstract: An apparatus comprising strings of non-volatile memory cells is disclosed. Each string comprises non-volatile memory cells, an operative select gate, and a dummy select gate. The apparatus comprises a select line connected to the operative select gate of each string, and a dummy line connected to the dummy select gate of each string. The dummy line is an immediate neighbor to the select line. The apparatus comprises a control circuit configured to apply a voltage waveform to the select line while the dummy line is floating. The control circuit is configured to detect a floating voltage on the dummy line while applying the voltage waveform to the select line. The control circuit is configured to determine a condition of the voltage waveform at a target location on the select line based on the floating voltage on the dummy line.

公开(公告)号：US20200258571A1

公开(公告)日：2020-08-13

申请号：US16829888

申请日：2020-03-25

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Huai-Yuan Tseng ,  Deepanshu Dutta

IPC: G11C11/56 ,  G11C16/04 ,  G11C16/34 ,  G11C16/10

Abstract: Apparatuses, systems, and methods are disclosed for adjusting a programming setting such as a programming voltage of a set of non-volatile storage cells, such as an SLC NAND array. The non-volatile storage cells may be arranged into a plurality of word lines. A subset of the non-volatile storage cells may be configured to store a programming setting. An on-die controller may be configured to read the programming setting from the setting subset, and write data to the non-volatile storage cells, using the programming setting. The on-die controller may further be configured to determine that the programming setting causes suboptimal programming of one or more of the non-volatile storage cells, and in response to the determination, store a revised programming setting on the setting subset.

公开(公告)号：US20200243138A1

公开(公告)日：2020-07-30

申请号：US16842112

申请日：2020-04-07

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Huai-Yuan Tseng ,  Deepanshu Dutta

IPC: G11C16/04 ,  G11C11/56 ,  G06F11/10 ,  G11C16/10 ,  G11C16/08 ,  G06F11/18

Abstract: Techniques for fast programming and read operations for memory cells. A first set of bit lines is connected to a first set of NAND strings and is interleaved with a second set of bit lines connected to a second set of NAND strings. The first set of NAND strings can be programmed by driving a voltage on the first set of bit lines while floating a voltage on the second set of bit lines, to reduce an inter-bit line capacitance and provide a relatively high access speed and a relatively low storage density (e.g., bits per memory cell). The second set of NAND strings can be programmed by concurrently driving a voltage on the first and second sets of bit lines, to provide a relatively low access speed and a relatively high storage density.

公开(公告)号：US10707226B1

公开(公告)日：2020-07-07

申请号：US16453268

申请日：2019-06-26

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Brian Murphy ,  Lito De La Rama

IPC: G11C16/34 ,  H01L27/1157 ,  G11C16/08 ,  G11C16/12 ,  G11C16/04

Abstract: A source side programming method and system are provided. A bad trigger block, of a plurality of blocks of a memory array, may be detected by determining a threshold voltage distribution of a drain side select gate of a block and determining whether the distribution is abnormal. If the distribution is abnormal, the block is a bad trigger block which may cause a failure in another block. IF the block is a bad trigger block, source side programming is performed on at least one word line of the bad trigger block by applying a non-zero voltage to at least one source side word line of the bad trigger block via a source side line.

公开(公告)号：US10468111B1

公开(公告)日：2019-11-05

申请号：US15967270

申请日：2018-04-30

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Huai-Yuan Tseng ,  Deepanshu Dutta

IPC: G11C7/00 ,  G11C16/34 ,  G11C16/04 ,  G11C16/26 ,  G11C16/10 ,  G11C11/56

Abstract: Systems and methods reduce device peak current during a read operation by charging control lines of a first set of memory cells faster than control lines of a second set of memory cells while minimizing the channel gradient formed adjacent to a selected word line to suppress occurrences of an injection read disturb in a sense line channel. For example, a first set of memory cells are in a first location relative to a selected memory cell selected for sensing, and a second set of memory cells are in a second location relative to the selected memory cell. The charge device is configured to charge the first set of memory cells and the second set of memory cells. In some aspects, a rate of charging the first set of memory cells is different from a rate of charging the second set of memory cells.

公开(公告)号：US20190318792A1

公开(公告)日：2019-10-17

申请号：US15952752

申请日：2018-04-13

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Huai-Yuan Tseng ,  Deepanshu Dutta

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/04 ,  H01L27/11556 ,  H01L27/11582

Abstract: Apparatuses and techniques are described for optimizing a program operation in a memory device. A storage location stores programing data for each word line, such as a program voltage for a set of memory cells. The set of memory cells may be periodically evaluated to determine updated programming setting(s). In one approach, the evaluation involves repeatedly sensing the set of memory cells between a program pulse and a verify signal in a program loop. The word line voltage can be stepped down to an intermediate voltage, then ramped down at a controlled rate while repeatedly sensing the memory cells, such as to detect an upper or lower tail of a threshold voltage distribution. The position of the tail can indicate a degree of over programming and this information can be used to adjust the programming setting(s) in a subsequent program operation.