公开(公告)号：US20240105262A1

公开(公告)日：2024-03-28

申请号：US17952857

申请日：2022-09-26

Applicant: SanDisk Technologies LLC

Inventor： Ramy Nashed Bassely Said ,  Jiahui Yuan ,  Lito De La Rama

IPC: G11C16/04 ,  G06F3/06 ,  G11C16/08 ,  G11C16/14 ,  G11C16/26

CPC classification number: G11C16/0483 ,  G06F3/0619 ,  G06F3/0652 ,  G06F3/0659 ,  G06F3/0679 ,  G11C16/08 ,  G11C16/14 ,  G11C16/26 ,  H01L25/0657

Abstract: To reduce data disturbs and lower current requirements of a 3D NAND memory die, a multi-block plane of non-volatile memory cells has its source line separated into multiple source line regions by introduction of isolation trenches. The plane structure for the NAND memory is maintained, but is broken into multi-block sub-planes, each with an independently biasable source line.

公开(公告)号：US20240047000A1

公开(公告)日：2024-02-08

申请号：US17873617

申请日：2022-07-26

Applicant: SanDisk Technologies LLC

Inventor： Yi Song ,  Lito De La Rama ,  Xiaochen Zhu

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/16

CPC classification number: G11C16/3445 ,  G11C16/0483 ,  G11C16/16

Abstract: An erase process for a group of non-volatile memory cells comprises applying doses of erasing to the group and performing erase verify between pairs of successive doses of erasing. The time needed to complete the erase process can be reduced by optimizing the order of performing erase verify. For example, erase verify can be performed by separately performing erase verify for multiple portions of the group in order from previously determined slowest erasing portion of the group to previously determined fastest erasing portion of the group, and aborting the performing of erase verify prior to completion of erase verify for all of the portions of the group in response to a number erase errors exceeding a limit.

公开(公告)号：US20230420055A1

公开(公告)日：2023-12-28

申请号：US17847553

申请日：2022-06-23

Applicant: SanDisk Technologies LLC

Inventor： Yihang Liu ,  Xiaochen Zhu ,  Lito De La Rama ,  Feng Gao

IPC: G11C16/16 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34

CPC classification number: G11C16/16 ,  G11C16/102 ,  G11C16/26 ,  G11C16/3404

Abstract: To prevent loss of data due to a word line to memory hole short (or another defect), it is proposed to perform an erase process for a plurality of memory cells, detect that a subset of the plurality of memory cells are slow to erase, and prevent successfully programming for at least some of the memory cells that are slow to erase. This technique uses the erase process to predict future word line to memory hole shorts and prevent programming of memory cells predicted to have a future word line to memory hole short so no data will be lost when the short manifests.

公开(公告)号：US12087373B2

公开(公告)日：2024-09-10

申请号：US17873617

申请日：2022-07-26

Applicant: SanDisk Technologies LLC

Inventor： Yi Song ,  Lito De La Rama ,  Xiaochen Zhu

IPC: G11C16/00 ,  G11C16/04 ,  G11C16/16 ,  G11C16/34

CPC classification number: G11C16/3445 ,  G11C16/0483 ,  G11C16/16

Abstract: An erase process for a group of non-volatile memory cells comprises applying doses of erasing to the group and performing erase verify between pairs of successive doses of erasing. The time needed to complete the erase process can be reduced by optimizing the order of performing erase verify. For example, erase verify can be performed by separately performing erase verify for multiple portions of the group in order from previously determined slowest erasing portion of the group to previously determined fastest erasing portion of the group, and aborting the performing of erase verify prior to completion of erase verify for all of the portions of the group in response to a number erase errors exceeding a limit.

公开(公告)号：US10707226B1

公开(公告)日：2020-07-07

申请号：US16453268

申请日：2019-06-26

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Brian Murphy ,  Lito De La Rama

IPC: G11C16/34 ,  H01L27/1157 ,  G11C16/08 ,  G11C16/12 ,  G11C16/04

Abstract: A source side programming method and system are provided. A bad trigger block, of a plurality of blocks of a memory array, may be detected by determining a threshold voltage distribution of a drain side select gate of a block and determining whether the distribution is abnormal. If the distribution is abnormal, the block is a bad trigger block which may cause a failure in another block. IF the block is a bad trigger block, source side programming is performed on at least one word line of the bad trigger block by applying a non-zero voltage to at least one source side word line of the bad trigger block via a source side line.

公开(公告)号：US12046294B2

公开(公告)日：2024-07-23

申请号：US17847553

申请日：2022-06-23

Applicant: SanDisk Technologies LLC

Inventor： Yihang Liu ,  Xiaochen Zhu ,  Lito De La Rama ,  Feng Gao

IPC: G11C11/34 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/34

CPC classification number: G11C16/16 ,  G11C16/102 ,  G11C16/26 ,  G11C16/3404

Abstract: To prevent loss of data due to a word line to memory hole short (or another defect), it is proposed to perform an erase process for a plurality of memory cells, detect that a subset of the plurality of memory cells are slow to erase, and prevent successfully programming for at least some of the memory cells that are slow to erase. This technique uses the erase process to predict future word line to memory hole shorts and prevent programming of memory cells predicted to have a future word line to memory hole short so no data will be lost when the short manifests.

公开(公告)号：US20240233847A1

公开(公告)日：2024-07-11

申请号：US18357274

申请日：2023-07-24

Applicant: SanDisk Technologies LLC

Inventor： Yi Song ,  Jiahui Yuan ,  Xiaochen Zhu ,  Lito De La Rama

IPC: G11C29/02 ,  G11C29/52

CPC classification number: G11C29/021 ,  G11C29/022 ,  G11C29/52

Abstract: A non-volatile memory system detects a memory operation failure. In response to the memory operation failure, the system determines whether adjusting an overdrive voltage applied to a word line avoids the memory operation failure. If adjusting the overdrive voltage applied to the word line avoids the memory operation failure, then future memory operations are performed by applying the adjusted overdrive voltage to the word line.

公开(公告)号：US20240177778A1

公开(公告)日：2024-05-30

申请号：US18357436

申请日：2023-07-24

Applicant: SanDisk Technologies LLC

Inventor： Yihang Liu ,  Xiaochen Zhu ,  Peng Wang ,  Jie Liu ,  Lito De La Rama ,  Feng Gao ,  Xiaoyu Yang

IPC: G11C16/12 ,  G11C16/04 ,  G11C16/08 ,  G11C16/34

CPC classification number: G11C16/12 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/3495

Abstract: A non-volatile storage apparatus includes non-volatile memory cells, word lines connected to the non-volatile memory cells, and a control circuit connected to the word lines and the memory cells. The word lines include data word lines and dummy word lines. Memory cells connected to data word lines are configured to store host data. Memory cells connected to dummy word lines do not store host data. The control circuit is configured to erase, program and read the memory cells. Errors from threshold voltage up-shifting in the memory cells connected to dummy word lines is prevented by adjusting the voltage applied to dummy word lines.

公开(公告)号：US11955184B2

公开(公告)日：2024-04-09

申请号：US17740429

申请日：2022-05-10

Applicant: SanDisk Technologies LLC

Inventor： Jiacen Guo ,  Xiaochen Zhu ,  Xiang Yang ,  Lito De La Rama ,  Yi Song ,  Jiahui Yuan

IPC: G11C16/28 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34

CPC classification number: G11C16/28 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3459

Abstract: Technology is disclosed herein for a memory system that compensates for different programming speeds in two sets of memory cells when reading those two sets of memory cells. The memory system programs a group of the memory cells to one or more data states. In one aspect, the memory cells are not verified during programming. The group has a first set of memory cells that program at a first speed and a second set of memory cells that program at a second speed. The memory system reads the first set of the memory cells with a first set of read parameters and reads the second set of the memory cells with a second set of read parameters. The first set of read parameters are different from the second set of read parameters to compensate for the different programming speeds.

公开(公告)号：US12119065B2

公开(公告)日：2024-10-15

申请号：US17709762

申请日：2022-03-31

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Xiaochen Zhu ,  Lito De La Rama ,  Yi Song ,  Jiacen Guo ,  Jiahui Yuan

IPC: G11C16/10 ,  G11C11/56 ,  G11C16/04 ,  G11C16/14 ,  G11C16/34 ,  H01L25/065 ,  H10B43/27

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C11/5671 ,  G11C16/14 ,  G11C16/3459 ,  H01L25/0657 ,  H01L2225/06562 ,  H10B43/27

Abstract: A non-volatile memory system limits the amount of programming for a first type of group of non-volatile memory cells based on a first parameter such that a maximum number of programming pulses applied to the first type of group of non-volatile memory cells to program to the last data state after the first type of group of non-volatile memory cells completed programming to the other data states is X programming pulses. The non-volatile memory system limits the amount of programming for a second type of group of the non-volatile memory cells based on a second parameter such that a maximum number of programming pulses applied to the second type of group of non-volatile memory cells to program to the last data state after the second type of group of non-volatile memory cells completed programming to the other data states is Y programming pulses.