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    Tuning Threshold Voltage in Field-Effect Transistors
    123.
    发明申请
    Tuning Threshold Voltage in Field-Effect Transistors 有权

    公开(公告)号：US20220181467A1

    公开(公告)日：2022-06-09

    申请号：US17676691

    申请日：2022-02-21

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hsueh Wen Tsau ,  Ziwei Fang ,  Huang-Lin Chao ,  Kuo-Liang Sung

    IPC: H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L23/28 ,  H01L21/82 ,  H01L21/56

    Abstract: A semiconductor structure includes an interfacial layer disposed over a semiconductor layer, a high-k gate dielectric layer disposed over the interfacial layer, where the high-k gate dielectric layer includes a first metal, a metal oxide layer disposed between the high-k gate dielectric layer and the interfacial layer, where the metal oxide layer is configured to form a dipole moment with the interfacial layer, and a metal gate stack disposed over the high-k gate dielectric layer. The metal oxide layer includes a second metal different from the first metal, and a concentration of the second metal decreases from a top surface of the high-k gate dielectric layer to the interface between the high-k gate dielectric layer and the interfacial layer.

    Metal gate structures of semiconductor devices
    126.
    发明授权
    Metal gate structures of semiconductor devices 有权

    公开(公告)号：US11264503B2

    公开(公告)日：2022-03-01

    申请号：US16718862

    申请日：2019-12-18

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chung-Liang Cheng ,  Ziwei Fang

    IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/06 ,  H01L27/088

    Abstract: A method of fabricating a semiconductor device includes forming first and second nanostructured layers arranged in an alternating configuration on a substrate, forming first and second nanostructured channel regions in the first nanostructured layers, forming first and second gate-all-around structures wrapped around each of the first and second nanostructured channel regions. The forming the GAA structures includes depositing first and second gate barrier layers having similar material compositions and work function values on the first and second gate dielectric layers, forming first and second diffusion barrier layers on the first and second gate barrier layers, and doping the first and second gate barrier layers from a dopant source layer through the first and second diffusion barrier layers. The first diffusion barrier layer is thicker than the second diffusion barrier layer and the doped first and second gate barrier layers have work function values and doping concentrations different from each other.

    Tuning threshold voltage in field-effect transistors
    127.
    发明授权
    Tuning threshold voltage in field-effect transistors 有权

    公开(公告)号：US11257923B2

    公开(公告)日：2022-02-22

    申请号：US16573733

    申请日：2019-09-17

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hsueh Wen Tsau ,  Ziwei Fang ,  Huang-Lin Chao ,  Kuo-Liang Sung

    IPC: H01L21/02 ,  H01L21/82 ,  H01L21/56 ,  H01L21/28 ,  H01L21/32 ,  H01L21/768 ,  H01L29/66 ,  H01L29/78 ,  H01L23/28

    Abstract: A method includes removing a dummy gate structure to form a gate trench over a semiconductor layer, forming a high-k gate dielectric layer over an interfacial layer exposed in the gate trench, depositing a metal-containing precursor over the high-k gate dielectric layer to form a metal-containing layer, and subsequently depositing an aluminum-containing precursor over the metal-containing layer, where depositing the aluminum-containing precursor forms an aluminum oxide layer at an interface between the high-k gate dielectric layer and the interfacial layer and where the metal-containing precursor includes a metal different from aluminum. The method further includes, subsequent to depositing the aluminum-containing precursor, removing a portion of the metal-containing layer, depositing a work-function metal layer over a remaining portion of the metal-containing layer, and forming a bulk conductive layer over the work-function metal layer, resulting in a metal gate structure.

    SEMICONDUCTOR DEVICE WITH MULTI-THRESHOLD GATE STRUCTURE
    130.
    发明申请
    SEMICONDUCTOR DEVICE WITH MULTI-THRESHOLD GATE STRUCTURE 有权

    公开(公告)号：US20210249517A1

    公开(公告)日：2021-08-12

    申请号：US16785919

    申请日：2020-02-10

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chung-Liang Cheng ,  Peng-Soon Lim ,  Ziwei Fang ,  Huang-Lin Chao

    IPC: H01L29/423 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/66 ,  H01L29/49

    Abstract: The present disclosure describes a semiconductor device that includes a substrate and a first transistor on the substrate. The first transistor includes a first gate structure and the first gate structure includes a gate dielectric layer and a first work function layer on the gate dielectric layer. The first gate structure also includes a capping layer on the first work function layer. The semiconductor device also includes a second transistor on the substrate, in which the second transistor includes a second gate structure. The second gate structure includes the gate dielectric layer and a second work function layer on the gate dielectric layer. The second gate structure also includes the first work function layer on the second work function layer and the silicon capping layer on the first work function layer.

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