公开(公告)号：US08897400B2

公开(公告)日：2014-11-25

申请号：US10838234

申请日：2004-05-05

Applicant: Dirk Felbach

Inventor： Dirk Felbach

IPC: H04L27/06 ,  G06F1/04

CPC classification number: G06F1/04 ,  G06F1/0328

Abstract: An arrangement and method for digital frequency synthesis. The arrangement includes a device for phase quantization structured and arranged to operate based on a reference clock and a phase increment value, and a device for amplitude quantization structured and arranged to operate based on a reference clock and a phase increment value. The arrangement also includes a device for noise shaping of a phase arranged in the signal path after the device for phase quantization, a device for noise shaping of an amplitude arranged in a signal path after the device for amplitude quantization, and a phase to amplitude converter.

Abstract translation: 一种用于数字频率合成的装置和方法。 该装置包括用于相位量化的装置，其被构造和布置为基于参考时钟和相位增量值进行操作，以及用于基于参考时钟和相位增量值进行结构和布置以进行操作的振幅量化装置。 该装置还包括用于在用于相位量化的装置之后布置在信号路径中的相位的噪声整形的装置，用于振幅量化的装置之后布置在信号路径中的幅度的噪声整形装置，以及相位到幅度转换器 。

公开(公告)号：US08572143B2

公开(公告)日：2013-10-29

申请号：US12614872

申请日：2009-11-09

Applicant: Thomas Dippon ,  Clemens Rabenstein

Inventor： Thomas Dippon ,  Clemens Rabenstein

IPC: H03B21/00

CPC classification number: G06F1/0328

Abstract: An output signal is generated from a received input data stream representing a sequence of digital data values. For each group of successive data values in the sequence of data values, a respective waveform pattern is assigned in dependence of the data content of the respective group of successive data values. The output signal is generated by generating the assigned respective waveform patterns corresponding to the input data stream.

Abstract translation: 从接收到的表示一系列数字数据值的输入数据流产生输出信号。 对于数据值序列中的每组连续数据值，根据相应组的连续数据值的数据内容分配相应的波形图案。 通过产生与输入数据流相对应的分配的各个波形图来产生输出信号。

公开(公告)号：US20120200326A1

公开(公告)日：2012-08-09

申请号：US13367834

申请日：2012-02-07

Applicant: Alexander Buhmann ,  Marian Keck

Inventor： Alexander Buhmann ,  Marian Keck

IPC: H03L7/08 ,  H03L7/00

CPC classification number: G06F1/0342 ,  G01C19/5776 ,  G06F1/022 ,  G06F1/0328 ,  H03L7/0991

Abstract: A method for reducing signal edge jitter in an output signal from a numerically controlled oscillator includes processing an input signal with a first accumulator to provide a first accumulator output signal and continuing to use a carry in the processing of the input signal with the first accumulator in the event of an overflow. The method further includes processing the input signal with a second accumulator to provide a second accumulator output signal and rejecting a carry in the processing of the input signal with the second accumulator in the event of an overflow. The method further includes outputting the second accumulator output signal at an output of the numerically controlled oscillator and synchronizing the second accumulator using the first accumulator output signal.

Abstract translation: 一种用于减少来自数控振荡器的输出信号中的信号边缘抖动的方法包括：利用第一累加器处理输入信号，以提供第一累加器输出信号，并且继续使用与第一累加器对输入信号进行处理的进位 发生溢出事件。 该方法还包括利用第二累加器来处理输入信号以在溢出的情况下提供第二累加器输出信号并且拒绝与第二累加器的输入信号的处理中的进位。 该方法还包括在数控振荡器的输出处输出第二累加器输出信号，并使用第一累加器输出信号使第二累加器同步。

公开(公告)号：US20110109349A1

公开(公告)日：2011-05-12

申请号：US12614872

申请日：2009-11-09

Applicant: Thomas Dippon ,  Clemens Rabenstein

Inventor： Thomas Dippon ,  Clemens Rabenstein

IPC: H03B21/00

CPC classification number: G06F1/0328

Abstract: An output signal is generated from a received input data stream representing a sequence of digital data values. For each group of successive data values in the sequence of data values, a respective waveform pattern is assigned in dependence of the data content of the respective group of successive data values. The output signal is generated by generating the assigned respective waveform patterns corresponding to the input data stream.

Abstract translation: 从接收到的表示一系列数字数据值的输入数据流产生输出信号。 对于数据值序列中的每组连续数据值，根据相应组的连续数据值的数据内容分配相应的波形图案。 通过产生与输入数据流相对应的分配的各个波形图来产生输出信号。

公开(公告)号：US07912882B2

公开(公告)日：2011-03-22

申请号：US10561558

申请日：2004-07-26

Applicant: In Gon Kim

Inventor： In Gon Kim

IPC: G06F1/08

CPC classification number: G06F1/0328 ,  H03L7/06

Abstract: The present invention relates to an apparatus for generating clock pulses using a Direct Digital Synthesizer (DDS). The present invention seeks to solve the problems of the conventional clock generator using a Phase Locked Loop (PLL) circuit where the output clock frequency cannot be varied and the output clock signal is degraded because of jitter and phase noise. The claimed apparatus comprises a phase accumulator, a phase-to-magnitude converter, a Digital-to-Analog (DA) converter, a band pass filter, and a comparator, which are serially connected. A 10×PLL multiplier provides a 196.608 MHz clock signal to the phase accumulator, the phase-magnitude converter and the digital analog converter, respectively. The phase accumulator also receives a Frequency Tuning Word (FTW) and using this FTW and the 196.608 MHz clock, outputs a desired specific frequency value. This frequency value is processed through the phase-magnitude converter, the digital analog converter, a band pass filter and a comparator in order to become a square wave of a desired frequency with a low jitter.

Abstract translation: 本发明涉及使用直接数字合成器（DDS）产生时钟脉冲的装置。 本发明寻求解决传统时钟发生器使用锁相环（PLL）电路的问题，其中输出时钟频率不能改变，并且输出时钟信号由于抖动和相位噪声而降级。 所要求保护的装置包括串联连接的相位累加器，相位到幅度转换器，数模（DA）转换器，带通滤波器和比较器。 10×PLL乘法器分别向相位累加器，相位幅度转换器和数字模拟转换器提供196.608MHz的时钟信号。 相位累加器还接收频率调谐字（FTW），并使用该FTW和196.608 MHz时钟输出所需的特定频率值。 该频率值通过相位幅度转换器，数字模拟转换器，带通滤波器和比较器进行处理，以便成为具有低抖动的期望频率的方波。

公开(公告)号：US07890562B2

公开(公告)日：2011-02-15

申请号：US11529837

申请日：2006-09-29

Applicant: David M. Gross ,  William Scott McDonald

Inventor： David M. Gross ,  William Scott McDonald

IPC: G06F1/02

CPC classification number: G06F1/0328 ,  G06F1/0353 ,  G06F1/0356

Abstract: An automatic test system that includes low cost and accurate circuitry for generating sinusoidal signals. Each sinusoidal signal generator includes a look-up table that can, for each phase on sine wave, output two digital values representing an in-phase and a quadrature-phase value of the sine wave. Simple circuitry can be used to address the look-up table to output in-phase and quadrature-phase values. The in-phase and quadrature-phase values can be applied to down-stream circuitry, such as error correction circuitry, that uses an in-phase and a quadrature-phase value to process the sine wave without the need for a relatively complex phase shifter in the down-stream circuitry. A dual-port memory may be used to implement the look-up table so that both an in-phase and a quadrature-phase value may be obtained from a single block of memory that stores a representation of a sine wave.

Abstract translation: 一种自动测试系统，包括用于产生正弦信号的低成本和精确电路。 每个正弦信号发生器包括查找表，对于正弦波上的每个相位，可以输出表示正弦波的同相和正交相位值的两个数字值。 可以使用简单的电路来寻址查找表，以输出同相和正交相位值。 同相和正交相位值可以应用于下行电路，例如误差校正电路，其使用同相和正交相位值来处理正弦波，而不需要相对复杂的移相器 在下游电路中。 可以使用双端口存储器来实现查找表，使得可以从存储正弦波的表示的单个存储器块获得同相和正交相位值。

公开(公告)号：US07818359B2

公开(公告)日：2010-10-19

申请号：US11532686

申请日：2006-09-18

Applicant: Nobuhiro Yoshizawa

Inventor： Nobuhiro Yoshizawa

IPC: G06F7/38 ,  G06K9/46

CPC classification number: G06F1/0328 ,  G06F1/0342

Abstract: In order to output amplitude data with the clock frequency higher than the clock frequency of phase data, the direct digital synthesizer for transmission and detection comprises: a transmitting phase for outputting a first phase data with a first clock frequency; a curtailing unit for outputting a second phase data with a second clock frequency smaller than the first clock frequency, and outputting additional data for compensating for phase information disappeared with curtailing process; an interpolating unit for outputting a third phase data with a third clock frequency larger than the first frequency by implementing interpolating process to the second phase data, and a detecting waveform for outputting amplitude data in accordance with the third phase data. The detecting signal amplitude data can be outputted with the third clock frequency higher than the second clock frequency of the second phase data transmitted.

Abstract translation: 为了输出时钟频率高于相位数据的时钟频率的振幅数据，用于传输和检测的直接数字合成器包括：用于输出具有第一时钟频率的第一相位数据的发送相位; 用于输出具有小于第一时钟频率的第二时钟频率的第二相位数据的压缩单元，并且输出用于补偿相位信息的附加数据，该相位信息通过缩减处理消失; 内插单元，用于通过对第二相位数据进行内插处理，输出具有大于第一频率的第三时钟频率的第三相位数据;以及检测波形，用于根据第三相位数据输出幅度数据。 检测信号幅度数据可以以高于所发送的第二相数据的第二时钟频率的第三时钟频率输出。

公开(公告)号：US07460628B2

公开(公告)日：2008-12-02

申请号：US11012192

申请日：2004-12-16

Applicant: Akihiro Suzuki ,  Hiroshi Sonobe

Inventor： Akihiro Suzuki ,  Hiroshi Sonobe

IPC: H04L7/00

CPC classification number: G06F1/0328 ,  H04N5/126

Abstract: A synchronous clock generation apparatus including a multiplier for multiplying a horizontal synchronizing signal by a horizontal synchronizing pulse signal to generate multiplication data, a gain variable digital LPF for extracting only DC components from the multiplication data and capable of performing gain adjustment, and a controller for calculating gain adjustment data, lock center frequency setting data, and LPF gain adjustment data based on the correction data. The controller detects an amount of deviation from the lock center frequency and an amount of variation, displaces the lock center frequency and shifts the lock range along the frequency axis to enlarge the apparent lock range when the amount of deviation is large, and reduces the gain to improve lock precision when the amount of variation is small, without expanding bits in the circuit configuration.

Abstract translation: 一种同步时钟生成装置，包括：乘法器，用于将水平同步信号乘以水平同步脉冲信号以产生乘法数据;增益可变数字LPF，用于仅从所述乘法数据中提取DC分量并且能够执行增益调整;以及控制器， 基于校正数据计算增益调整数据，锁定中心频率设定数据和LPF增益调整数据。 控制器检测与锁定中心频率的偏差量和变化量，使锁定中心频率移位，并且沿着频率轴移动锁定范围，以在偏差量大时扩大视在锁定范围，并且减小增益 当变化量小时，提高锁定精度，而不会在电路配置中扩展位。

公开(公告)号：US07284025B2

公开(公告)日：2007-10-16

申请号：US10739591

申请日：2003-12-18

Applicant: Steven K. Sullivan ,  Raymond L. Veith ,  Iwao Akiyama ,  Yasumasa Fujisawa

Inventor： Steven K. Sullivan ,  Raymond L. Veith ,  Iwao Akiyama ,  Yasumasa Fujisawa

IPC: G06F1/02

CPC classification number: G06F1/0328

Abstract: A DDS pulse generator has an accumulator that accumulates a phase increment value to produce phase accumulator values, and has a lookup table that contains a digital representation of a pulse waveform such that a pulse output signal is produced from the lookup table in response to the phase accumulator values. To change a period of the pulse output signal without changing edge positions a programmable modulo value is used. An address mapper is situated between the accumulator and address lines of the lookup table to map the rising and falling edge portions of the phase accumulator values into large regions of the lookup table, while phase accumulator values corresponding to high and low logic levels are mapped into small regions of the lookup table. The resulting pulse output signal has easily independently controlled period and pulse width as well as rising and falling edge speeds. By making better use of the lookup table it is possible to generate very narrow pulses with low repetition rates or pulses in which the rise time and fall time are very different from the period.

Abstract translation: DDS脉冲发生器具有累加相位增量值以产生相位累加器值的累加器，并且具有包含脉冲波形的数字表示的查找表，使得响应于相位从查找表产生脉冲输出信号 累加器值。 为了改变脉冲输出信号的周期而不改变边沿位置，使用可编程的模数值。 地址映射器位于查找表的累加器和地址线之间，以将相位累加器值的上升沿和下降沿部分映射到查找表的大区域，而对应于高逻辑电平和低逻辑电平的相位累加器值映射到 查找表的小区域。 所产生的脉冲输出信号容易独立地控制周期和脉冲宽度以及上升和下降沿速度。 通过更好地利用查找表，可以产生具有低重复率或脉冲的非常窄的脉冲，其中上升时间和下降时间与周期非常不同。

公开(公告)号：US20070164793A1

公开(公告)日：2007-07-19

申请号：US10561558

申请日：2004-07-26

Applicant: In Gon Kim

Inventor： In Gon Kim

IPC: H03B21/00

CPC classification number: G06F1/0328 ,  H03L7/06

Abstract: The present invention relates to an apparatus for generating clock pulses using a Direct Digital Synthesizer (DDS). The present invention seeks to solve the problems of the conventional clock generator using a Phase Locked Loop (PLL) circuit where the output clock frequency cannot be varied and the output clock signal is degraded because of jitter and phase noise. The claimed apparatus comprises a phase accumulator, a phase-to-magnitude converter, a Digital-to-Analog (DA) converter, a band pass filter, and a comparator, which are serially connected. A 10× PLL multiplier provides a 196.608MHz clock signal to the phase accumulator, the phase-magnitude converter and the digital analog converter, respectively. The phase accumulator also receives a Frequency Tuning Word (FTW) and using this FTW and the 196.608MHz clock, outputs a desired specific frequency value. This frequency value is processed through the phase-magnitude converter, the digital analog converter, a band pass filter and a comparator in order to become a square wave of a desired frequency with a low jitter.

Abstract translation: 本发明涉及使用直接数字合成器（DDS）产生时钟脉冲的装置。 本发明寻求解决传统时钟发生器使用锁相环（PLL）电路的问题，其中输出时钟频率不能改变，并且输出时钟信号由于抖动和相位噪声而降级。 所要求保护的装置包括串联连接的相位累加器，相位到幅度转换器，数模（DA）转换器，带通滤波器和比较器。 10倍PLL乘法器分别向相位累加器，相位幅度转换器和数字模拟转换器提供196.608MHz的时钟信号。 相位累加器还接收频率调谐字（FTW），并使用该FTW和196.608MHz时钟输出所需的特定频率值。 该频率值通过相位幅度转换器，数字模拟转换器，带通滤波器和比较器进行处理，以便成为具有低抖动的期望频率的方波。