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公开(公告)号：US20240080431A1
公开(公告)日：2024-03-07
申请号：US18273280
申请日：2022-01-13
IPC分类号： H04N13/279 , G06T7/50 , G06T15/00 , G06V10/74 , H04N13/128
CPC分类号： H04N13/279 , G06T7/50 , G06T15/00 , G06V10/761 , H04N13/128
摘要： An image synthesis apparatus comprises a first receiver (201) receiving three dimensional image data describing at least part of a three dimensional scene and second receiver (203) receiving a view pose for a viewer. An image region circuit (207) determines at least a first image region in the three dimensional image data and a depth circuit (209) determines a depth indication for the first image region from depth data of the three dimensional image data. A region circuit (211) determines a first region for the first image region. A view synthesis circuit (205) generates a view image from the three dimensional image data where the view image representing a view of the three dimensional scene from the view pose. The view synthesis circuit (205) is arranged to adapt a transparency for the first image region in the view image in response to the depth indication and a distance between the view pose and the first region.
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公开(公告)号：US20240078737A1
公开(公告)日：2024-03-07
申请号：US18320792
申请日：2023-05-19
发明人： Jian LIANG , Andrew Evan GRUBER , Tao WANG , Xuefeng TANG , Vishwanath Shashikant NIKAM , Nigel POOLE , Kalyan Kumar BHIRAVABHATLA , Fei XU , Zilin YING
IPC分类号： G06T15/00
CPC分类号： G06T15/005
摘要： A sliced graphics processing unit (GPU) architecture in processor-based devices is disclosed. In some aspects, a GPU based on a sliced GPU architecture includes multiple hardware slices. The GPU further includes a command processor (CP) circuit and an unslice primitive controller (PC_US). Upon receiving a graphics instruction from a central processing unit (CPU), the CP circuit determines a graphics workload, and transmits the graphics workload to the PC_US. The PC_US then partitions the graphics workload into multiple subbatches and distributes each subbatch to a PC_S of a hardware slice for processing.
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公开(公告)号：US20240078736A1
公开(公告)日：2024-03-07
申请号：US18262008
申请日：2022-04-21
发明人： Zhongyuan LIU
IPC分类号： G06T15/00
CPC分类号： G06T15/005
摘要： A hair model rendering method, including: obtaining hair data of hair model and storing hair data in video memory of graphics processor; configuring stream processor unit corresponding to each hairline data group; loading the current to-be-processed hair node data in corresponding hairline data and linked hair node data associated with to-be-processed hair node data, to register of graphics processor via thread; determining a set of parameter-node position solving algorithms corresponding to to-be-processed hair node data; solving position by the current node-position solving algorithm and corresponding parameter node; and saving hair node data corresponding to the current parameter node to video memory of graphics processor, when the current node-position solving algorithm completes position solving based on the current parameter node, and if the current parameter node does not belong to parameter node of other node-position algorithms or node-position solving algorithm group corresponding to other hair node data in hairline data.
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公开(公告)号：US20240078735A1
公开(公告)日：2024-03-07
申请号：US18067837
申请日：2022-12-19
发明人： Jian Liang , Andrew Evan Gruber , Tao Wang , Xuefeng Tang , Vishwanath Shashikant Nikam , Nigel Poole , Kalyan Kumar Bhiravabhatla , Fei Xu , Zilin Ying
IPC分类号： G06T15/00
CPC分类号： G06T15/005
摘要： A sliced graphics processing unit (GPU) architecture in processor-based devices is disclosed. In some aspects, a GPU based on a sliced GPU architecture includes multiple hardware slices. The GPU further includes a command processor (CP) circuit and an unslice primitive controller (PC_US). Upon receiving a graphics instruction from a central processing unit (CPU), the CP circuit determines a graphics workload, and transmits the graphics workload to the PC_US. The PC_US then partitions the graphics workload into multiple subbatches and distributes each subbatch to a PC_S of a hardware slice for processing.
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公开(公告)号：US20240077910A1
公开(公告)日：2024-03-07
申请号：US18388357
申请日：2023-11-09
发明人： Kunio HOSOYA
CPC分类号： G06F1/1652 , G06F1/1694 , G06F3/011 , G06F3/0484 , G06T13/20 , G06T15/005 , H04M1/0268 , G06F2200/1637 , G06F2203/04102
摘要： An electronic device is provided which displays an object (body) on a flexible display screen in accordance with a three-dimensional shape of the display screen by utilizing the flexibility of the display screen. An electronic device including a display portion which includes a flexible display device displaying an object on a display screen; a detection portion detecting positional data of a given part of the display screen; and an arithmetic portion calculating a three-dimensional shape of the display screen on the basis of the positional data and computing motion of the object to make the object move according to a given law in accordance with the calculated three-dimensional shape of the display screen.
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公开(公告)号：US11922555B2
公开(公告)日：2024-03-05
申请号：US18122042
申请日：2023-03-15
发明人： Diego Jesus , John W. Howson , Panagiotis Velentzas , Robert Brigg , Xile Yang
IPC分类号： G06T15/00 , G06T1/20 , G06T1/60 , G06T9/00 , G06T11/20 , G06T11/40 , G06T15/04 , G06T17/10 , G06T17/20
CPC分类号： G06T15/005 , G06T1/20 , G06T1/60 , G06T9/00 , G06T11/20 , G06T11/40 , G06T15/00 , G06T15/04 , G06T17/10 , G06T17/20 , G06T2210/12
摘要： Methods and tiling engines for tiling primitives in a tile based graphics processing system in which a rendering space is divided into a plurality of tiles. The method includes generating a multi-level hierarchy of tile groups, each level of the multi-level hierarchy comprising one or more tile groups comprising one or more of the plurality of tiles; receiving a plurality of primitive blocks, each primitive block comprising geometry data for one or more primitives; associating each of the plurality of primitive blocks with one or more of the tile groups up to a maximum number of tile groups such that if at least one primitive of a primitive block falls, at least partially, within the bounds of a tile, the primitive block is associated with at least one tile group that includes that tile; and generating a control stream for each tile group based on the associations, wherein each control stream comprises a primitive block entry for each primitive block associated with the corresponding tile group.
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公开(公告)号：US20240070982A1
公开(公告)日：2024-02-29
申请号：US18503976
申请日：2023-11-07
申请人： Aurora Solar Inc.
CPC分类号： G06T17/05 , G06T15/005 , G06T17/20 , G06T19/20 , G06T2219/2021
摘要： Described herein is a process and system for constructing three-dimensional (3D) representations of roof structures. The system can create representations of roof structures of arbitrary complexity and can create representations of dependent roof structures such as dormers. The system can create representations of roof structures that conventional methods cannot create, such as roofs with edges that are not coplanar, roofs with faces that do not connect to exterior edges, roofs composed of sub-structures, or roofs with dependent structures such as dormers.
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公开(公告)号：US20240070962A1
公开(公告)日：2024-02-29
申请号：US18190084
申请日：2023-03-25
IPC分类号： G06T15/00
CPC分类号： G06T15/005
摘要： A graphics processing method and system are disclosed. The system includes multiple cores with a master mode core and at least one slave mode core, where the master mode core is configured to construct primitives according to input geometry data, split the constructed primitives into primitive core groups, and distribute the primitive core groups to the master mode core and the at least one slave mode core; and the master mode core and the at least one slave mode core are configured to process the distributed primitive core groups to obtain a rendered image. The system and method of the present disclosure provide powerful parallel data processing capability, which allows for processing of a massive amount of geometry data, and enable excellent performance by taking actual working states of hardware into full consideration.
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129.发明公开公开(公告)号：US20240070960A1
公开(公告)日：2024-02-29
申请号：US17900192
申请日：2022-08-31
发明人： Mark S. GROSSMAN
CPC分类号： G06T15/005 , G06T15/06 , G06T15/08
摘要： Systems and methods for ray tracing acceleration structure level of detail processing are described. An example graphics processing system is to retrieve a first level of detail value for a sub-tree from a level of detail residency map corresponding to a bounding volume hierarchy of objects. The graphics processing system is to determine a second level of detail value for the sub-tree. The graphics processing system is to select a final level of detail value for the sub-tree based on a comparison between the first level of detail value for the sub-tree and the second level of detail value for the sub-tree. The graphics processing system is to, based on the final level of detail value for the sub-tree, select child nodes in an acceleration structure tree and trace the selected child nodes.
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公开(公告)号：US11915357B2
公开(公告)日：2024-02-27
申请号：US16820483
申请日：2020-03-16
申请人： Intel Corporation
CPC分类号： G06T15/005 , G06T15/06
摘要： Apparatus and method for stack throttling. For example, one embodiment of an apparatus comprises: execution circuitry comprising a plurality of functional units to execute a plurality of ray shaders and generate a plurality of primary rays and a corresponding plurality of ray messages; a first in first out (FIFO) buffer to queue the ray messages generated by the EUs; a cache to store one or more of the plurality of primary rays; a memory-backed stack to store a first subset of the plurality of ray messages in a corresponding plurality of entries; memory-backed stack management circuitry to either store a second subset of the plurality of ray messages to the memory-backed stack, or to temporarily store the one or more the second subset of the plurality of ray messages to a memory subsystem based, at least in part, on a number of entries currently occupied by ray messages in the memory-backed stack; and ray traversal circuitry to read a next ray message from the memory-backed stack, retrieve a next primary ray identified by the ray message from the cache or a memory subsystem, and perform traversal operations on the next primary ray.
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