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公开(公告)号：US10706196B2
公开(公告)日：2020-07-07
申请号：US16207457
申请日：2018-12-03
Inventor： Dominik Lubeley , Heiko Kalte
IPC: G06F17/50 , G06F30/34 , G06F30/39 , G06F30/327 , G06F16/903 , G06F16/901 , G06F117/06
Abstract: A method for generating an FPGA implementation based on an FPGA design serving as an FPGA model and/or a hardware description, including the steps of synthesizing a net list from the FPGA design and generating the FPGA implementation from the net list. The method includes searching for a similar FPGA implementation, the step of generating the FPGA implementation from the net list takes place using the similar FPGA implementation, the method includes a step of generating a graph-based representation based on the FPGA design, and the step of searching for a similar FPGA implementation comprises comparing the graph-based representation of the FPGA design with a graph-based representation of the at least one similar FPGA implementation. A method for generating a bit stream based on an FPGA design is also provided, serving as an FPGA model and/or a hardware description.
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公开(公告)号：US10671783B2
公开(公告)日：2020-06-02
申请号：US16207457
申请日：2018-12-03
Inventor： Dominik Lubeley , Heiko Kalte
IPC: G06F17/50 , G06F30/34 , G06F30/39 , G06F30/327 , G06F16/903 , G06F16/901 , G06F117/06
Abstract: A method for generating an FPGA implementation based on an FPGA design serving as an FPGA model and/or a hardware description, including the steps of synthesizing a net list from the FPGA design and generating the FPGA implementation from the net list. The method includes searching for a similar FPGA implementation, the step of generating the FPGA implementation from the net list takes place using the similar FPGA implementation, the method includes a step of generating a graph-based representation based on the FPGA design, and the step of searching for a similar FPGA implementation comprises comparing the graph-based representation of the FPGA design with a graph-based representation of the at least one similar FPGA implementation. A method for generating a bit stream based on an FPGA design is also provided, serving as an FPGA model and/or a hardware description.
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133.发明授权公开(公告)号：US10657037B2
公开(公告)日：2020-05-19
申请号：US16119718
申请日：2018-08-31
Inventor： Joerg Hagendorf , Martin Kronmueller
Abstract: A configuration system for a test device designed for testing an electronic control unit. The test device is a hardware-in-the-loop simulator or a rapid control prototyping simulator, wherein a software model of a technical system is executed on the test device and the software model communicates electronically via an input/output interface of the test device with a system to be tested that is connected to the test device. Simulation data is electronically transmitted by the communication, and the configuration system is coupled to a modeling system and in the modeling system is a software model characterized by transversely and longitudinally connected function blocks. The configuration system configures the test device by interconnected configuration items such that the configuration items determine the physical characteristics of the input/output interface and/or the connection of the input/output interface with the software model.
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134.发明授权公开(公告)号：US10572369B2
公开(公告)日：2020-02-25
申请号：US15474060
申请日：2017-03-30
Inventor： Thorsten Hufnagel
Abstract: A method for monitoring errors when testing a control program of a control device in a simulation environment, the control program being executed by an emulator on a computer, the emulator assigning an extended range of items to program variables of the control program, a variable value allocated to a program variable being stored in the extended range of items, the emulator marking program variables as erroneous or non-erroneous, the marking being carried out on the basis of an assignment of non-erroneous program variables to a first category and of erroneous program variables to a second category, or the marking being carried out on the basis of an error field stored in the extended range of items, a validity value being allocated to the error field of a non-erroneous program variable and an error value being allocated to the error field, of an erroneous program variable.
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135.发明授权公开(公告)号：US10551807B2
公开(公告)日：2020-02-04
申请号：US15233187
申请日：2016-08-10
Inventor： Holger Naundorf
IPC: G05B17/02
Abstract: A method is provided for connecting an input/output interface of a tester equipped for control unit development to a model of a technical system present in the tester using an already-existing basic test model of a control unit. The input/output interface is designed for connecting a hardware implementation of the control unit or for connecting a technical system to be controlled, and the model to be connected to the input/output interface is a test model of the technical system to be controlled or a test model of the control unit. The already-existing basic test model of the control unit is accessed, and at least one communication requirement is extracted from the basic test model of the control unit.
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Patent Agency Ranking
公开(公告)号：US10521332B1
公开(公告)日：2019-12-31
申请号：US16145208
申请日：2018-09-28
Inventor： Joerg Sauer
Abstract: A method for parametrization of a simulation model includes: composing the simulation model based on placement of elementary blocks and line connectors between the elementary blocks; adding a first marker block containing a first digital identifier to a first subsystem in the simulation model; adding a second marker block containing a second digital identifier to a second subsystem in the simulation model; analyzing the simulation model; listing parameters of the simulation model in a hierarchical tree and displaying the hierarchical tree on a screen to facilitate altering the parameters of the simulation model via the hierarchical tree; and determining whether to list the first subsystem and the second subsystem in a common node of the hierarchical tree or in separate nodes of the hierarchical tree based on whether or not the first digital identifier and the second digital identifier are identical.
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137.发明申请公开(公告)号：US20190196925A1
公开(公告)日：2019-06-27
申请号：US16226730
申请日：2018-12-20
Inventor： Tully ERNST
CPC classification number: G06F11/261 , G05B17/02 , G05B2219/23445 , G05B2219/23446 , G05B2219/23451 , G06F11/3672 , G06F17/5009
Abstract: A configuration system for configuring a test system suitable for testing an electronic control unit, wherein a configuration diagram has a plurality of hierarchy elements, and a hierarchy element either has one hierarchy element or multiple hierarchy elements or no hierarchy element. The hierarchy element has an identifier, and wherein a hierarchy element has port(s) or no port, and wherein at least one hierarchy element is assigned to a functional property of the test system to be configured, wherein in an expanded view mode, the hierarchy elements are displayed at least partially nested and the ports and identifiers are shown one below the other, wherein in an at least partially collapsed view mode, a first set of hierarchy elements is shown such that the identifiers are shown side by side, wherein the ports and identifiers remain visible and the hierarchical relationship of the hierarchy elements remains displayed.
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公开(公告)号：US10331804B2
公开(公告)日：2019-06-25
申请号：US15097318
申请日：2016-04-13
Inventor： Andreas Himmler , Matthias Klemm
Abstract: A system for testing at least a first automatic control device via a plant model includes: a first subsystem; and a second subsystem which is spatially separated from the first subsystem. The plant model comprises an executable first model code and an executable second model code. The first subsystem comprises a first time-signal processing component configured to electronically assign a first time signal (Ts1) from a global time source to a first event. The first model code is configured to provide a first calculation result based on the first event. The second subsystem comprises a second time-signal processing component configured to electronically assign a second time signal (Ts2) from the global time source to a second event. The second model code is configured to provide a second calculation result based on the second event.
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公开(公告)号：US10268625B2
公开(公告)日：2019-04-23
申请号：US14996281
申请日：2016-01-15
Inventor： Rafael Gilles
Abstract: An input/output interface of a test device is configured, wherein the input/output interface is developed for connecting a hardware unit to a behavioral model present in the test device. The method includes the steps of: displaying a graphical representation of the input/output interface as a signal path between a hardware port for connection of the hardware and at least one model port for connecting the behavioral model via a selectable input/output function; receiving a first configuration for the signal path; receiving a test value that is predefinable at the hardware port or the model port of the signal path, but, for example, is also predefinable through the graphical representation of the hardware port or the model port; propagating a test signal associated with the test value along the signal path according to the first configuration for the signal path, and displaying the propagated test signal on the graphical representation of the model port or the hardware port.
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公开(公告)号：US10224930B2
公开(公告)日：2019-03-05
申请号：US15964245
申请日：2018-04-27
Inventor： Dominik Lubeley , Marc Schlenger , Heiko Kalte
IPC: H03K19/003 , H03K19/017 , G01R31/317 , H03K19/0175
Abstract: A method for detecting the topology of electrical wiring between at least two field-programmable gate arrays (FPGAs) includes implementing a first receive register on a second interface pin; implementing a first send register on a first driver; activating the first driver via a first activation signal; emitting, by the first driver, a first signal, wherein the first signal is defined by the first send register; reading out, by a first receive register, whether the first signal is received at the second interface pin; and allocating the second interface pin to the first interface pin if the first signal from the first driver is received at the second interface pin.
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