公开(公告)号：US20080025090A1

公开(公告)日：2008-01-31

申请号：US11870528

申请日：2007-10-11

Applicant: Sung-Soo LEE ,  Young-Ho LIM ,  Hyun-Chul CHO ,  Dong-Hyuk CHAE

Inventor： Sung-Soo LEE ,  Young-Ho LIM ,  Hyun-Chul CHO ,  Dong-Hyuk CHAE

IPC: G11C16/04

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C2211/5642

Abstract: According to one aspect, a memory cell array includes a bit line connected to a plurality of nonvolatile memory cells, where the nonvolatile memory cells are selectively programmable in any one of at least first, second, third and fourth threshold voltage states, and where the first, second, third and fourth threshold voltage states correspond to four different data values defined by first and second bits. A page buffer circuit stores a logic value as main latch data and is responsive to a main latch signal to selectively flip the logic value of the main latch data according to a voltage level of the bit line. A sub-latch circuit stores a logic value as sub-latch data and is responsive to a sub-latch signal to selectively flip the logic value of the sub-latch data according to the voltage level of the bit line. The memory device is operable in a read mode which reads the threshold voltage state of the non-volatile memory cells and a programming mode which programs the threshold voltage state of the non-volatile memory cells, wherein the page buffer circuit is selectively responsive to the sub-latch data to inhibit flipping of the logic value of the main latch data in the programming mode.

Abstract translation: 根据一个方面，存储单元阵列包括连接到多个非易失性存储单元的位线，其中非易失性存储单元可选择性地以至少第一，第二，第三和第四阈值电压状态中的任何一个编程，并且其中 第一，第二，第三和第四阈值电压状态对应于由第一和第二位定义的四个不同的数据值。 页面缓冲电路将逻辑值存储为主锁存数据，并且响应于主锁存信号，以根据位线的电压电平选择性地翻转主锁存数据的逻辑值。 子锁存电路将逻辑值存储为子锁存数据，并且响应于子锁存信号，以根据位线的电压电平选择性地翻转子锁存数据的逻辑值。 存储器件可读取读取非易失性存储器单元的阈值电压状态的读取模式和编程非易失性存储器单元的阈值电压状态的编程模式，其中页面缓冲器电路有选择地响应于 子锁存数据，以禁止在编程模式下翻转主锁存器数据的逻辑值。

公开(公告)号：US20080007159A1

公开(公告)日：2008-01-10

申请号：US11647664

申请日：2006-12-29

Applicant: Dong-Jin Seo ,  Sung-Soo Lee ,  Yong-Woo Lee

Inventor： Dong-Jin Seo ,  Sung-Soo Lee ,  Yong-Woo Lee

IPC: H01L51/00

CPC classification number: H01L51/529 ,  H01L51/5237

Abstract: An organic light-emitting diode (OLED) display device includes a display panel having an OLED element, a receiving container to receive the display panel, a driving circuit part that is disposed under the receiving container and drives the display panel, and a heat insulating member that is disposed between the display panel and the receiving container, and comprises a porous polymer. Deterioration of the light-emitting layer may be prevented and/or reduced to increase durability of the OLED display device.

Abstract translation: 有机发光二极管（OLED）显示装置包括具有OLED元件的显示面板，用于接收显示面板的接收容器，设置在接收容器下方并驱动显示面板的驱动电路部分，以及绝热 构件，其设置在显示面板和接收容器之间，并且包括多孔聚合物。 可以防止和/或减少发光层的劣化以增加OLED显示装置的耐久性。

公开(公告)号：US20070212525A1

公开(公告)日：2007-09-13

申请号：US11685524

申请日：2007-03-13

Applicant: Un-cheol Sung ,  Hoon Kim ,  Sang-pil Lee ,  Sung-soo Lee

Inventor： Un-cheol Sung ,  Hoon Kim ,  Sang-pil Lee ,  Sung-soo Lee

IPC: B05D5/00 ,  B32B23/02

CPC classification number: H01L51/5246 ,  G02F2001/133388 ,  H01L27/3244 ,  H01L51/5259 ,  Y10T428/24777 ,  Y10T428/24802

Abstract: A display device and method thereof which minimizes introduction of oxygen and moisture from the outside includes an insulating substrate, a display part formed on the insulating substrate, a cover substrate combined with the insulating substrate, a filler provided between the insulating substrate and the cover substrate, the filler includes a first region and a second region spaced from the first region and formed at a circumference of the first region, and a moisture absorbent formed in a space between the first region and the second region

Abstract translation: 最小化从外部引入氧气和水分的显示装置及其方法包括绝缘基板，形成在绝缘基板上的显示部分，与绝缘基板结合的盖基板，设置在绝缘基板和盖基板之间的填充物 所述填料包括与所述第一区域间隔开并且形成在所述第一区域的圆周处的第一区域和第二区域，以及形成在所述第一区域和所述第二区域之间的空间中的吸湿剂

公开(公告)号：US20070120468A1

公开(公告)日：2007-05-31

申请号：US11556610

申请日：2006-11-03

Applicant: Sung-Soo LEE ,  Jae-Hoon JUNG ,  Un-Cheol SUNG ,  Ji-Hye CHOI

Inventor： Sung-Soo LEE ,  Jae-Hoon JUNG ,  Un-Cheol SUNG ,  Ji-Hye CHOI

IPC: H01L51/00

CPC classification number: H01L51/56 ,  H01L51/0097 ,  H01L2251/5338

Abstract: The present invention discloses a display apparatus including: an insulating substrate, a metal film formed on a first surface of the insulating substrate and comprising a magnetic substance, a thin film transistor formed on a second surface of the insulating substrate, a first passivation film formed on the thin film transistor, a pixel electrode electrically connected with the thin film transistor and forming a pixel region, an organic layer formed on the pixel electrode, and a common electrode formed on the organic layer.

Abstract translation: 本发明公开了一种显示装置，包括：绝缘基板，形成在所述绝缘基板的第一表面上的金属膜，其包括磁性物质，形成在所述绝缘基板的第二表面上的薄膜晶体管，形成有第一钝化膜 在薄膜晶体管上，与薄膜晶体管电连接并形成像素区域的像素电极，形成在像素电极上的有机层和形成在有机层上的公共电极。

公开(公告)号：US5848009A

公开(公告)日：1998-12-08

申请号：US946471

申请日：1997-10-07

Applicant: Sung-soo Lee ,  Young-ho Lim

Inventor： Sung-soo Lee ,  Young-ho Lim

IPC: G11C29/44 ,  G11C29/00 ,  G11C7/00 ,  G11C8/00

CPC classification number: G11C29/765

Abstract: Integrated circuit memory devices and operating methods map a plurality of memory cell blocks excluding defective memory cell blocks into a continuous address sequence of variable length. The memory cell blocks excluding the defective memory cell blocks, are preferably mapped to defective normal memory cell blocks, beginning at a highest memory cell block address and sequentially proceeding to lower cell block addresses, so as to generate continuous addresses for the memory cell blocks. Continuous address spaces may be provided by providing a plurality of flag blocks, a respective one of which corresponds to a respective one of the normal memory cell blocks. Each flag block contains a first indication that the corresponding normal memory cell block is nondefective, a second indication that the corresponding normal memory cell block is substituted with a redundant memory cell block, or a third indication that the corresponding normal memory cell block is substituted with another normal memory cell block. Then, upon addressing a normal memory cell block, a redundant memory cell block is substituted if the second indication is in the flag block that is associated with the selected normal memory cell block. A nondefective normal memory cell block is substituted for a selected normal cell block in response to the third indication being in the flag block that is associated with the selected normal memory cell block.

Abstract translation: 集成电路存储器件和操作方法将排除不良存储器单元块的多个存储单元块映射成可变长度的连续地址序列。 排除缺陷存储单元块的存储单元块优选地映射到从最高存储器单元块地址开始的有缺陷的正常存储单元块，并且顺序地进行到较低单元块地址，以便为存储单元块生成连续地址。 可以通过提供多个标志块来提供连续地址空间，其中相应的标志块对应于正常存储器单元块中的相应一个。 每个标志块包含对应的正常存储器单元块是无缺陷的第一指示，相应的正常存储器单元块被冗余存储单元块代替的第二指示，或相应的正常存储器单元块被替换的第三指示 另一个正常的存储单元块。 然后，在寻址正常存储器单元块时，如果第二指示位于与所选择的常规存储器单元块相关联的标志块中，则替换冗余存储器单元块。 响应于与所选择的正常存储器单元块相关联的标志块中的第三指示，替代无缺陷的正常存储器单元块以选择的正常单元块。

公开(公告)号：US5699306A

公开(公告)日：1997-12-16

申请号：US593203

申请日：1996-01-29

Applicant: Sung-Soo Lee ,  Jin-Ki Kim

Inventor： Sung-Soo Lee ,  Jin-Ki Kim

IPC: G11C17/00 ,  G11C16/06 ,  G11C29/00 ,  G11C29/04 ,  G11C13/00

CPC classification number: G11C29/70

Abstract: A redundant circuit for EEPROMs which is capable of replacing defective normal memory cells with redundant memory cells in a wafer state as well as in a packaged state. The nonvolatile semiconductor memory includes an array having normal row blocks and redundant row blocks. A normal row decoder selects one of the normal row blocks, and a normal row decoder disable circuit disables the normal row decoder in response to a redundant array selection command. A redundant row block selection circuit selects one of the redundant row blocks in response to the redundant array selection command and an external address. First and second redundant latch circuits are provided for storing programmed addresses corresponding to defective normal row blocks. The second redundant latch circuit is programmed when first redundant row blocks are defective, and is capable of being programmed in a package state. Thereafter, a redundant address overlap selection prevention circuit prevents both the first and second redundant row blocks from being selected when the defective normal row block address is specified, and enables only the second redundant row block to be selected instead.

Abstract translation: 一种用于EEPROM的冗余电路，其能够以晶圆状态以及处于封装状态的冗余存储单元替换有缺陷的正常存储单元。 非易失性半导体存储器包括具有正常行块和冗余行块的阵列。 正常行解码器选择正常行块之一，并且正常行解码器禁止电路响应冗余阵列选择命令禁用正常行解码器。 冗余行块选择电路响应于冗余阵列选择命令和外部地址来选择冗余行块中的一个。 提供第一和第二冗余锁存电路用于存储对应于有缺陷的正常行块的编程地址。 当第一冗余行块有缺陷时，第二冗余锁存电路被编程，并且能够被编程在封装状态。 此后，冗余地址重叠选择防止电路防止当指定了有缺陷的正常行块地址时选择第一和第二冗余行块，并且仅使能第二冗余行块。

公开(公告)号：US5642309A

公开(公告)日：1997-06-24

申请号：US526422

申请日：1995-09-11

Applicant: Jin-Ki Kim ,  Hyung-Kyu Lim ,  Sung-Soo Lee

Inventor： Jin-Ki Kim ,  Hyung-Kyu Lim ,  Sung-Soo Lee

IPC: G11C17/00 ,  G11C16/02 ,  G11C16/06 ,  G11C16/10 ,  G11C16/30 ,  G11C29/00 ,  G11C29/12 ,  G11C7/00 ,  G11C16/04

CPC classification number: G11C16/10 ,  G11C16/30

Abstract: An auto-program voltage generator in a nonvolatile semiconductor memory having a plurality of floating gate type memory cells, program circuit for programming selected memory cells, and program verification circuit for verifying whether or not the selected memory cells are successfully programmed comprises a high voltage generator for generating a program voltage, a trimming circuit for detecting the level of the program voltage to increase sequentially the program voltage within a predetermined voltage range every time the selected memory cells are not successfully programmed, a comparing circuit for comparing the detected voltage level with a reference voltage and then generating a comparing signal, and a high voltage generation control circuit for activating the high voltage generator in response to the comparing signal.

Abstract translation: 一种具有多个浮动型存储单元的非易失性半导体存储器中的自动编程电压发生器，用于编程所选存储单元的程序电路和用于验证所选存储单元是否被成功编程的程序验证电路包括高电压发生器 用于产生编程电压的微调电路，用于检测编程电压的电平以在每次所选存储单元未成功编程时在预定电压范围内依次增加编程电压的微调电路;用于将检测的电压电平与 参考电压，然后产生比较信号;以及高电压发生控制电路，用于响应于比较信号激活高电压发生器。