公开(公告)号：US09224685B1

公开(公告)日：2015-12-29

申请号：US13416137

申请日：2012-03-09

申请人： Weiqi Ding ,  Wilson Wong ,  Shuxian Chen ,  Jeffrey T. Watt

发明人： Weiqi Ding ,  Wilson Wong ,  Shuxian Chen ,  Jeffrey T. Watt

IPC分类号： H01L23/522 ,  H01L49/02

CPC分类号： H01L23/5226 ,  H01L23/522 ,  H01L23/5223 ,  H01L23/5225 ,  H01L28/82 ,  H01L28/86 ,  H01L2924/0002 ,  H01L2924/00

摘要： A metal-oxide-metal (MOM) capacitor structure is disclosed. The MOM capacitor includes a plurality of layers, each layer having a plurality of electrodes. The plurality of electrodes, separated by oxide layers, forms a first plate and a second plate of the MOM capacitor. The plurality of electrodes on each of the layers is coupled to a plurality of electrodes on an adjacent layer through a plurality of vias. A shield layer is coupled to each of the electrodes that forms the second plate of the MOM capacitor on each of the plurality of layers.

摘要翻译： 公开了一种金属氧化物金属（MOM）电容器结构。 MOM电容器包括多个层，每层具有多个电极。 由氧化物层分隔开的多个电极形成MOM电容器的第一板和第二板。 每个层上的多个电极通过多个通孔耦合到相邻层上的多个电极。 屏蔽层耦合到在多个层中的每一层上形成MOM电容器的第二板的每个电极。

公开(公告)号：US08989214B2

公开(公告)日：2015-03-24

申请号：US12002539

申请日：2007-12-17

申请人： Weiqi Ding ,  Mengchi Liu ,  Wilson Wong ,  Sergey Shumarayev

发明人： Weiqi Ding ,  Mengchi Liu ,  Wilson Wong ,  Sergey Shumarayev

IPC分类号： H04L12/66 ,  H04L25/03 ,  H04L7/00

CPC分类号： H04L25/03885 ,  H04L7/0054 ,  H04L25/03019 ,  H04L25/03878

摘要： Circuitry for receiving a high-speed serial data signal (e.g., having a bit rate in the range of about 10 Gpbs and higher) includes a two-stage, continuous-time, linear equalizer having only two serially connected stages. Phase detector circuitry may be provided for receiving the serial output of the equalizer and for converting successive pairs of bits in that output to successive parallel-form bit pairs. Further demultiplexing circuitry may be provided to demultiplex successive groups of the parallel-form bit pairs to final groups of parallel bits, which can be quite large in terms of number of bits (e.g., 64 parallel bits). Another aspect of the invention relates to multiplexer circuitry for efficiently going in the opposite direction from such relatively large groups of parallel data bits to a high-speed serial data output signal.

公开(公告)号：US08898029B1

公开(公告)日：2014-11-25

申请号：US13046626

申请日：2011-03-11

申请人： Wilson Wong ,  Allen Chan

发明人： Wilson Wong ,  Allen Chan

IPC分类号： G01D18/00

CPC分类号： G06F1/26 ,  G06F1/10

摘要： An integrated circuit is presented. The integrated circuit includes a selection circuit that selects a reference voltage and an output voltage associated with a number of adjustable voltage regulators connected to the selection circuit. The integrated circuit also has an analog to digital converter, which converts the selected output voltage and the reference voltage to a digital representation. An analog state machine of the integrated circuit receives the digital representation from the analog to digital converter and compares the selected output voltage with the reference voltage.

摘要翻译： 介绍了一个集成电路。 集成电路包括选择电路，其选择参考电压和与连接到选择电路的多个可调电压调节器相关联的输出电压。 集成电路还具有模数转换器，其将所选输出电压和参考电压转换为数字表示。 集成电路的模拟状态机从模数转换器接收数字表示，并将选择的输出电压与参考电压进行比较。

公开(公告)号：US08860469B1

公开(公告)日：2014-10-14

申请号：US13549228

申请日：2012-07-13

申请人： Weiqi Ding ,  Wilson Wong

发明人： Weiqi Ding ,  Wilson Wong

IPC分类号： H03B1/00 ,  H03K3/00

CPC分类号： G11C29/028 ,  G11C29/022

摘要： Disclosed are apparatus and methods to advantageously calibrate a transmitter output swing. One embodiment relates to a method for calibrating the output swing voltage of a transmitter. A fixed value is provided as the data input, and output swing calibration circuitry is connected to the transmitter buffer circuit. A transmitter current is set to an initial level, and the transmitter current is adjusted until the output swing of the transmitter buffer circuit is calibrated. Another embodiment relates to an integrated circuit which includes a transmitter buffer circuit, output swing calibration circuitry, and switches arranged to electrically connect the transmitter buffer circuit to the output swing calibration circuitry during an output swing calibration mode. Another embodiment relates to an output swing calibration circuit which includes comparison circuitry and logic and control circuitry.

摘要翻译： 公开了有利地校准发射机输出摆幅的装置和方法。 一个实施例涉及用于校准发射机的输出摆幅电压的方法。 提供固定值作为数据输入，输出摆幅校准电路连接到发送器缓冲电路。 发射机电流被设置为初始电平，并且调整发射机电流直到校准发射机缓冲器电路的输出摆幅。 另一个实施例涉及一种集成电路，其包括发射器缓冲电路，输出摆幅校准电路和布置成在输出摆幅校准模式期间将发射器缓冲电路电连接到输出摆幅校准电路。 另一个实施例涉及一种包括比较电路和逻辑和控制电路的输出摆幅校准电路。

公开(公告)号：US08787352B2

公开(公告)日：2014-07-22

申请号：US13103132

申请日：2011-05-09

申请人： Sergey Shumarayev ,  Bill W. Bereza ,  Chong H. Lee ,  Rakesh H. Patel ,  Wilson Wong

发明人： Sergey Shumarayev ,  Bill W. Bereza ,  Chong H. Lee ,  Rakesh H. Patel ,  Wilson Wong

IPC分类号： H04L12/28 ,  H04L5/14 ,  H04L27/00

CPC分类号： H04L5/14 ,  H03K19/17744 ,  H04L27/00

摘要： High-speed serial data transceiver circuitry on a programmable logic device (“PLD”) includes some channels that are able to operate at data rates up to a first, relatively low maximum data rate, and other channels that are able to operate at data rates up to a second, relatively high maximum data rate. The relatively low-speed channels are served by relatively low-speed phase locked loop (“PLL”) circuitry, and have other circuit components that are typically needed for handling data that is transmitted at relatively low data rates. The relatively high-speed channels are served by relatively high-speed PLLs, and have other circuit components that are typically needed for handling data that is transmitted at relatively high data rates.

摘要翻译： 可编程逻辑器件（“PLD”）上的高速串行数据收发器电路包括一些能够以高达第一，相对较低的最大数据速率的数据速率工作的通道，以及能够以数据速率操作的其他通道 达到第二个相对较高的最大数据速率。 相对低速的通道由相对低速的锁相环（“PLL”）电路服务，并且具有通常用于处理以相对低的数据速率发送的数据所需的其他电路组件。 相对高速的信道由相对高速的PLL服务，并且具有通常用于处理以相对高的数据速率传输的数据所需的其他电路部件。

公开(公告)号：US08767801B1

公开(公告)日：2014-07-01

申请号：US12729732

申请日：2010-03-23

申请人： Allen Chan ,  Wilson Wong

发明人： Allen Chan ,  Wilson Wong

IPC分类号： H04B1/38

CPC分类号： G01R31/31708 ,  G01R31/31709 ,  G01R31/31716

摘要： The ability of clock and data recovery (“CDR”) circuitry on an integrated circuit (“IC”) to handle jitter in a serial data input signal can be tested by using transmitter circuitry on the IC to produce a serial data output signal whose time base has been subjected to modulation. Loop-back circuitry on the IC may be used to apply the serial data output signal to the CDR circuitry as the serial data input signal of the CDR circuitry. Modulation circuitry on the IC may be used to cause the above modulation of the time base of the serial data output signal.

摘要翻译： 集成电路（“IC”）上的时钟和数据恢复（“CDR”）电路处理串行数据输入信号中的抖动的能力可以通过使用IC上的发射器电路来测试，以产生串行数据输出信号，其时间 基地已经进行调制。 可以使用IC上的环回电路将串行数据输出信号作为CDR电路的串行数据输入信号施加到CDR电路。 可以使用IC上的调制电路来对串行数据输出信号的时基进行上述调制。

公开(公告)号：US08536919B1

公开(公告)日：2013-09-17

申请号：US12909781

申请日：2010-10-21

申请人： Allen Chan ,  Wilson Wong

发明人： Allen Chan ,  Wilson Wong

IPC分类号： H03K3/00

CPC分类号： H03K3/0375 ,  H03K3/356139

摘要： Integrated circuits with communications circuitry are provided. The communications circuitry may include at least first and second flip-flops connected in a chain along a data path. The first flip-flop may be controlled by a clock signal. The clock signal may be fed to a delay matching circuit. The delay matching circuit may provide a delayed version of the clock signal that controls the second flip-flop. The delay provided by the delay matching circuit may be equal to a clock-to-output delay of the first flip-flop. The delay matching circuit may have the same physical arrangement as the first flip-flop. The first and second flip-flops and the delay matching circuit may include dynamic sense amplifier flip-flops. The delay matching circuit may have an input that receives a high signal, a control input that receives the clock signal, and an output over which the delayed clock signal is provided.

摘要翻译： 提供具有通信电路的集成电路。 通信电路可以包括沿着数据路径连接在链中的至少第一和第二触发器。 第一触发器可以由时钟信号控制。 时钟信号可以馈送到延迟匹配电路。 延迟匹配电路可以提供控制第二触发器的时钟信号的延迟版本。 由延迟匹配电路提供的延迟可以等于第一触发器的时钟到输出延迟。 延迟匹配电路可以具有与第一触发器相同的物理布置。 第一和第二触发器和延迟匹配电路可以包括动态读出放大器触发器。 延迟匹配电路可以具有接收高信号的输入端，接收时钟信号的控制输入端和提供延迟时钟信号的输出端。

公开(公告)号：US08446172B2

公开(公告)日：2013-05-21

申请号：US13102918

申请日：2011-05-06

申请人： Allen Chan ,  Wilson Wong

发明人： Allen Chan ,  Wilson Wong

IPC分类号： H03K19/0175

CPC分类号： H04B3/06 ,  H04L25/0272 ,  H04L25/03343

摘要： One embodiment relates to a method of driving a transmission signal with pre-emphasis having minimal voltage jitter. A digital data signal is received, and a pre-emphasis signal is generated. The pre-emphasis signal may be a phase shifted and scaled version of the digital data signal. An output signal is generated by adding the pre-emphasis signal to the digital data signal within a driver switch circuit while low-pass filtering is applied to current sources of the driver switch circuit. Other embodiments, aspects, and features are also disclosed.

摘要翻译： 一个实施例涉及一种驱动具有最小电压抖动的预加重的传输信号的方法。 接收数字数据信号，产生预加重信号。 预加重信号可以是数字数据信号的相移和缩放版本。 通过在驱动器开关电路内的数字数据信号中加上预加重信号，同时对驱动器开关电路的电流源施加低通滤波来产生输出信号。 还公开了其它实施例，方面和特征。

公开(公告)号：US20130009279A1

公开(公告)日：2013-01-10

申请号：US13617347

申请日：2012-09-14

申请人： Weiqi Ding ,  Sergey Shumarayev ,  Wilson Wong ,  Ali Atesoglu ,  Sharat Babu Ippili

发明人： Weiqi Ding ,  Sergey Shumarayev ,  Wilson Wong ,  Ali Atesoglu ,  Sharat Babu Ippili

IPC分类号： H01L27/08 ,  H01L21/20

CPC分类号： H03B5/1212 ,  H01F2021/125 ,  H01F2027/2809 ,  H01L2924/0002 ,  H03B5/1243 ,  H03B5/1268 ,  H01L2924/00

摘要： Integrated circuits with phase-locked loops are provided. Phase-locked loops may include an oscillator, a phase-frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, and a programmable divider. The voltage-controlled oscillator may include multiple inductors, an oscillator circuit, and a buffer circuit. A selected one of the multiple inductors may be actively connected to the oscillator circuit. The voltage-controlled oscillators may have multiple oscillator circuits. Each oscillator circuit may be connected to a respective inductor, may include a varactor, and may be powered by a respective voltage regulator. Each oscillator circuit may be coupled to a respective input transistor pair in the buffer circuit through associated coupling capacitors. A selected one of the oscillator circuits may be turned on during normal operation by supplying a high voltage to the selected one of the oscillator circuit and by supply a ground voltage to the remaining oscillator circuits.

摘要翻译： 提供具有锁相环的集成电路。 锁相环可以包括振荡器，相位频率检测器，电荷泵，环路滤波器，压控振荡器和可编程分频器。 压控振荡器可以包括多个电感器，振荡器电路和缓冲电路。 多个电感器中选择的一个可以主动地连接到振荡器电路。 压控振荡器可以具有多个振荡器电路。 每个振荡器电路可以连接到相应的电感器，可以包括变容二极管，并且可以由相应的电压调节器供电。 每个振荡器电路可以通过相关联的耦合电容器耦合到缓冲电路中的相应输入晶体管对。 所选择的一个振荡器电路可以在正常操作期间通过向所选振荡器电路中的一个提供高电压并且向剩余的振荡器电路提供接地电压而导通。

公开(公告)号：US08335249B1

公开(公告)日：2012-12-18

申请号：US12626379

申请日：2009-11-25

申请人： Xiaoyan Su ,  Sriram Narayan ,  Wilson Wong ,  Sergey Shumarayev

发明人： Xiaoyan Su ,  Sriram Narayan ,  Wilson Wong ,  Sergey Shumarayev

IPC分类号： H03H7/40

CPC分类号： H04L25/03878 ,  H04L25/0272 ,  H04L25/061

摘要： Equalizer circuitry on an integrated circuit (“IC”) includes first, second, and third continuous time, equalizer stages connected in series. Each stage includes peaking inductor circuitry. The equalizer circuitry may further include controllably variable, static, DC mode offset voltage compensation circuitry and/or dynamic, continuous mode, offset voltage compensation circuitry for respectively reducing DC voltage offset and/or time-varying, continuous mode voltage offset between an output of the third equalizer stage and utilization circuitry to which that output is applied. The first equalizer stage may be preceded by termination circuitry having controllably variable impedance. Differential circuitry and signalling may be used for various circuit components. The equalizer circuitry is particularly useful for fabrication as part of a programmable IC, using 28 nm CMOS technology, and as a receiver equalizer for a high-speed serial data signal having a bit rate of 20-25 Gbps.

摘要翻译： 集成电路（IC）上的均衡器电路包括串联连接的第一，第二和第三连续时间的均衡器级。 每个阶段包括峰值电感电路。 均衡器电路可以进一步包括可控制的，静态的，直流模式偏移电压补偿电路和/或动态连续模式偏移电压补偿电路，用于分别减小DC电压偏移和/或时变，连续模式电压偏移 应用该输出的第三均衡器级和利用电路。 第一均衡器级可以在具有可控制可变阻抗的终端电路之前。 差分电路和信令可用于各种电路组件。 均衡器电路对于使用28nm CMOS技术的可编程IC的一部分进行制造以及作为具有20-25Gbps的比特率的高速串行数据信号的接收机均衡器是特别有用的。