System and method of detecting cavitation in pumps

    公开(公告)号:US09777748B2

    公开(公告)日:2017-10-03

    申请号:US12753930

    申请日:2010-04-05

    CPC classification number: F04D29/669 F04D15/0077 F04D15/0088

    Abstract: A system and method for detecting cavitation in pumps for fixed and variable supply frequency applications is disclosed. The system includes a controller having a processor programmed to repeatedly receive real-time operating current data from a motor driving a pump, generate a current frequency spectrum from the current data, and analyze current data within a pair of signature frequency bands of the current frequency spectrum. The processor is further programmed to repeatedly determine fault signatures as a function of the current data within the pair of signature frequency bands, repeatedly determine fault indices based on the fault signatures and a dynamic reference signature, compare the fault indices to a reference index, and identify a cavitation condition in a pump based on a comparison between the reference index and a current fault index.

    SEMICONDUCTOR STRUCTURE AND RECESS FORMATION ETCH TECHNIQUE
    136.
    发明申请
    SEMICONDUCTOR STRUCTURE AND RECESS FORMATION ETCH TECHNIQUE 有权
    半导体结构和记忆形成蚀刻技术

    公开(公告)号:US20160064539A1

    公开(公告)日:2016-03-03

    申请号:US14442546

    申请日:2013-11-15

    Abstract: A semiconductor structure has a first layer that includes a first semiconductor material and a second layer that includes a second semiconductor material. The first semiconductor material is selectively etchable over the second semiconductor material using a first etching process. The first layer is disposed over the second layer. A recess is disposed at least in the first layer. Also described is a method of forming a semiconductor structure that includes a recess. The method includes etching a region in a first layer using a first etching process. The first layer includes a first semiconductor material. The first etching process stops at a second layer beneath the first layer. The second layer includes a second semiconductor material.

    Abstract translation: 半导体结构具有包括第一半导体材料的第一层和包括第二半导体材料的第二层。 第一半导体材料可以使用第一蚀刻工艺在第二半导体材料上选择性地蚀刻。 第一层设置在第二层上。 凹部至少设置在第一层中。 还描述了形成包括凹部的半导体结构的方法。 该方法包括使用第一蚀刻工艺蚀刻第一层中的区域。 第一层包括第一半导体材料。 第一蚀刻工艺在第一层下面的第二层停止。 第二层包括第二半导体材料。

    System and method to determine electric motor efficiency using an equivalent circuit
    137.
    发明授权
    System and method to determine electric motor efficiency using an equivalent circuit 有权
    使用等效电路确定电动机效率的系统和方法

    公开(公告)号:US09170303B2

    公开(公告)日:2015-10-27

    申请号:US13088846

    申请日:2011-04-18

    CPC classification number: G01R31/343 H02P23/14

    Abstract: A system and method for determining electric motor efficiency includes a monitoring system having a processor programmed to determine efficiency of an electric motor under load while the electric motor is online. The determination of motor efficiency is independent of a rotor speed measurement. Further, the efficiency is based on a determination of stator winding resistance, an input voltage, and an input current. The determination of the stator winding resistance occurs while the electric motor under load is online.

    Abstract translation: 用于确定电动机效率的系统和方法包括监视系统,其具有被编程为在电动机在线时确定负载下的电动机的效率的处理器。 电机效率的确定与转子速度测量无关。 此外,效率基于定子绕组电阻,输入电压和输入电流的确定。 定子绕组电阻的确定发生在负载下的电动机在线时。

    System and method employing a minimum distance and a load feature database to identify electric load types of different electric loads
    138.
    发明授权
    System and method employing a minimum distance and a load feature database to identify electric load types of different electric loads 有权
    采用最小距离的系统和方法和负载特征数据库来识别不同电力负载的电负荷类型

    公开(公告)号:US08918346B2

    公开(公告)日:2014-12-23

    申请号:US13304834

    申请日:2011-11-28

    CPC classification number: H02J13/00 H02J3/00

    Abstract: A method identifies electric load types of a plurality of different electric loads. The method includes providing a load feature database of a plurality of different electric load types, each of the different electric load types including a first load feature vector having at least four different load features; sensing a voltage signal and a current signal for each of the different electric loads; determining a second load feature vector comprising at least four different load features from the sensed voltage signal and the sensed current signal for a corresponding one of the different electric loads; and identifying by a processor one of the different electric load types by determining a minimum distance of the second load feature vector to the first load feature vector of the different electric load types of the load feature database.

    Abstract translation: 一种方法识别多个不同电负载的电负载类型。 该方法包括提供多种不同电负载类型的负载特征数据库,每种不同的电负载类型包括具有至少四个不同负载特征的第一负载特征向量; 感测每个不同电负载的电压信号和电流信号; 确定第二负载特征向量,其包括来自所感测的电压信号的至少四个不同的负载特征和用于所述不同电负载中的相应一个的感测的电流信号; 以及通过确定所述第二负载特征向量与所述负载特征数据库的不同电负载类型的所述第一负载特征向量的最小距离,由处理器识别所述不同电负载类型之一。

    Magnetic layer
    139.
    发明授权
    Magnetic layer 有权
    磁性层

    公开(公告)号:US08795764B1

    公开(公告)日:2014-08-05

    申请号:US12916302

    申请日:2010-10-29

    CPC classification number: G11B5/653 G11B5/64 G11B5/65 G11B5/84

    Abstract: An apparatus includes a substrate and a magnetic layer coupled to the substrate. The magnetic layer includes an alloy that has magnetic hardness that is a function of the degree of chemical ordering of the alloy. The degree of chemical ordering of the alloy in a first portion of the magnetic layer is greater than the degree of chemical ordering of the alloy in a second portion of the magnetic layer, and the first portion of the magnetic layer is closer to the substrate than the second portion of the magnetic layer.

    Abstract translation: 一种装置包括基板和耦合到该基板的磁性层。 磁性层包括具有作为合金的化学排序程度的函数的磁性硬度的合金。 合金在磁性层的第一部分中的化学排序程度大于磁性层第二部分中合金的化学排序程度,并且磁性层的第一部分比第二部分更靠近基体 磁性层的第二部分。

    Enhancement-mode nitride transistor
    140.
    发明授权
    Enhancement-mode nitride transistor 有权
    增强型氮化物晶体管

    公开(公告)号:US08759876B2

    公开(公告)日:2014-06-24

    申请号:US12574146

    申请日:2009-10-06

    CPC classification number: H01L29/7788 H01L29/2003 H01L29/51 H01L29/7787

    Abstract: A heterojunction for use in a transistor structure is provided. The heterojunction includes a barrier layer positioned beneath a gate region of the transistor structure. The barrier layer includes nitride-based semiconductor materials. A channel layer provides electrical conduction An intermediate layer near the barrier layer and including nitride-based semiconductor materials having a wider bandgap than the channel layer.

    Abstract translation: 提供了一种用于晶体管结构的异质结。 异质结包括位于晶体管结构的栅极区域下方的势垒层。 阻挡层包括氮化物基半导体材料。 沟道层提供电传导在阻挡层附近的中间层,并且包括具有比沟道层更宽的带隙的氮化物基半导体材料。

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