公开(公告)号：US4592022A

公开(公告)日：1986-05-27

申请号：US756707

申请日：1985-07-19

申请人： Katsuhiro Shimohigashi ,  Hiroo Masuda ,  Kunihiko Ikuzaki ,  Hiroshi Kawamoto

发明人： Katsuhiro Shimohigashi ,  Hiroo Masuda ,  Kunihiko Ikuzaki ,  Hiroshi Kawamoto

IPC分类号： G11C11/419 ,  G11C11/409 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/4097 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/8242 ,  H01L23/522 ,  H01L27/04 ,  H01L27/092 ,  H01L27/10 ,  H01L27/108 ,  G11C11/40 ,  G11C13/00

CPC分类号： G11C11/409 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/4097 ,  H01L23/522 ,  H01L27/108 ,  H01L27/10805 ,  H01L2924/0002 ,  H01L2924/3011 ,  Y10S148/164

摘要： A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of intersection between the data lines and the word lines. The RAM includes a P-type semiconductor substrate and an N-type well region formed in the substrate. The memory cells are disposed within the well, and the sense amplifier, which is connected to the data lines, is constructed of a pair of N-channel MOSFETs formed in the semiconductor substrate and a pair of P-channel MOSFETs formed in the well region.

公开(公告)号：US4564925A

公开(公告)日：1986-01-14

申请号：US535056

申请日：1983-09-23

申请人： Yoshiaki Onishi, deceased ,  by Junko Onishi, administratrix ,  Hiroshi Kawamoto ,  Tokumasa Yasui

发明人： Yoshiaki Onishi, deceased ,  by Junko Onishi, administratrix ,  Hiroshi Kawamoto ,  Tokumasa Yasui

IPC分类号： G11C11/403 ,  G11C11/4096 ,  G11C7/00

CPC分类号： G11C11/4096

摘要： A semiconductor memory has dynamic memory cells, such as one-MOS transistor cells, a detector circuit which detects changes in applied address signals, and a timing generator circuit which receives detection outputs of the detector circuit. When the address signals are changed, various timing signals are responsively produced from the timing generator circuit. In response to the timing signals generated in succession, data lines to which the memory cells are coupled are first precharged, and one of the memory cells is selected after the precharge of the data lines. Data delivered from the selected memory cell to the data line is amplified when the operation of a sense amplifier is started. The amplified data is supplied to an external terminal through a column switch, a main amplifier, an output amplifier, etc., which are similarly operated in succession. Since the semiconductor memory of this arrangement forms a pseudo-static memory, it requires only a small number of external timing signals. In order to obtain a desirable pseudo-static memory, a data line precharge level is equalized to half of the supply voltage level, and the sense amplifier is constructed of a CMOS-FET latch circuit. As a result, the period of time from the change of the address signals until the delivery of the output data can be sufficiently shortened. It is therefore possible to form a pseudo-static memory which is, in effect, regarded as a static memory.

摘要翻译： 半导体存储器具有诸如单MOS晶体管单元，检测所施加的地址信号的变化的检测器电路的动态存储单元以及接收检测器电路的检测输出的定时发生器电路。 当地址信号改变时，从定时发生器电路响应地产生各种定时信号。 响应于连续生成的定时信号，首先对存储器单元耦合的数据线进行预充电，并且在数据线的预充电之后选择一个存储单元。 当读出放大器的操作开始时，从选择的存储单元传送到数据线的数据被放大。 放大的数据通过类似地连续操作的列开关，主放大器，输出放大器等提供给外部端子。 由于这种布置的半导体存储器形成伪静态存储器，所以它仅需要少量的外部定时信号。 为了获得期望的伪静态存储器，将数据线预充电电平等于电源电压电平的一半，并且读出放大器由CMOS-FET锁存电路构成。 结果，能够充分地缩短从地址信号变更直到输出数据传送的时间。 因此，可以形成实际上被视为静态存储器的伪静态存储器。