公开(公告)号：US20220256149A1

公开(公告)日：2022-08-11

申请号：US17726133

申请日：2022-04-21

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi ABE ,  Takahiro NISHI ,  Tadamasa TOMA ,  Ryuichi KANOH ,  Chong Soon LIM ,  Ru Ling LIAO ,  Hai Wei SUN ,  Sughosh Pavan SHASHIDHAR ,  Han Boon TEO ,  Jing Ya LI

IPC: H04N19/119 ,  H04N19/52 ,  H04N19/176 ,  H04N19/137

Abstract: Provided is an encoder which includes circuitry and memory. Using the memory, the circuitry splits an image block into a plurality of partitions, obtains a prediction image for a partition, and encodes the image block using the prediction image. When the partition is not a non-rectangular partition, the circuitry obtains (i) a first prediction image for the partition, (ii) a gradient image for the first prediction image, and (iii) a second prediction image as the prediction image using the first prediction image and the gradient image. When the partition is a non-rectangular partition, the circuitry obtains the first prediction image as the prediction image without using the gradient image.

公开(公告)号：US20220201323A1

公开(公告)日：2022-06-23

申请号：US17476947

申请日：2021-09-16

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Ryuichi KANOH ,  Tadamasa TOMA ,  Takahiro NISHI ,  Kiyofumi ABE ,  Takashi HASHIMOTO

IPC: H04N19/513 ,  H04N19/159 ,  H04N19/186 ,  H04N19/182

Abstract: Provided is an encoder that achieves further improvement. The encoder includes processing circuitry and memory. Using the memory, the processing circuitry: obtains two prediction images from two reference pictures; derives a luminance gradient value of each pixel position in each of the two prediction images; derives a luminance local motion estimation value of each pixel position in a current block; generates a luminance final prediction image using a luminance value and the luminance gradient value in each of the two prediction images, and the luminance local motion estimation value of the current block; and generates a chrominance final prediction image using at least one of the luminance gradient value of each of the two prediction images or the luminance local motion estimation value of the current block, and chrominance of each of the two prediction images.

公开(公告)号：US20220201289A1

公开(公告)日：2022-06-23

申请号：US17693612

申请日：2022-03-14

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi ABE ,  Takahiro NISHI ,  Tadamasa TOMA ,  Ryuichi KANOH

IPC: H04N19/105 ,  H04N19/159 ,  H04N19/176 ,  H04N19/186

Abstract: An encoder includes memory and circuitry. The circuitry, using the memory, (i) selects a mode from among a plurality of modes each for deriving a motion vector, and derives a motion vector for a current block via the selected mode, and (ii) performs inter prediction encoding on the current block, using the derived motion vector, via one of a skip mode and a non-skip mode different from the skip mode. The plurality of modes include a plurality of first modes each for predicting the motion vector for the current block based on an encoded block neighboring the current block without encoding information indicating a motion vector into a stream. When a second mode included in the plurality of first modes is selected, the current block is encoded via the non-skip mode regardless of presence or absence of a residual coefficient.

公开(公告)号：US20220182648A1

公开(公告)日：2022-06-09

申请号：US17678608

申请日：2022-02-23

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Virginie DRUGEON ,  Tadamasa TOMA ,  Takahiro NISHI ,  Kiyofumi ABE ,  Yusuke KATO

IPC: H04N19/30 ,  H04N19/70

Abstract: An encoder includes memory and circuitry coupled to the memory. The circuitry is configured to: generate an encoded bitstream that includes a multi-layer structure; and store, in the encoded bitstream, a syntax element having a value indicating that a layer in the multi-layer structure to be output by a decoder is arbitrarily specified, the syntax element defining that at least one layer is to be output from among layers arbitrarily specifiable by the decoder.

公开(公告)号：US20220166995A1

公开(公告)日：2022-05-26

申请号：US17666932

申请日：2022-02-08

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Virginie DRUGEON ,  Tadamasa TOMA ,  Takahiro NISHI ,  Kiyofumi ABE ,  Yusuke KATO

IPC: H04N19/44 ,  H04N19/105 ,  H04N19/423 ,  H04N19/172

Abstract: An encoder includes circuitry and memory coupled to the circuitry. In operation, the circuitry encodes a hypothetical reference decoder (HRD) parameter into a buffering period supplemental enhancement information (SEI) message independently from a sequence parameter set. The HRD parameter is related to a decoding unit and an HRD.

公开(公告)号：US20220159304A1

公开(公告)日：2022-05-19

申请号：US17591259

申请日：2022-02-02

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Masato OHKAWA ,  Hideo SAITOU ,  Kiyofumi ABE ,  Takahiro NISHI ,  Tadamasa TOMA ,  Yusuke KATO

IPC: H04N19/60 ,  H04N19/30 ,  H04N19/186 ,  H04N19/12 ,  H04N19/17 ,  H04N19/184 ,  H04N19/119 ,  H04N19/112 ,  H04N19/16

Abstract: Provided is an encoder including: circuitry; and memory coupled to the circuitry. In operation, the circuitry: performs a mapping process of Luma Mapping with Chroma Scaling (LMCS) for transforming a first pixel value space applied to a luma display image signal into a second pixel value space applied to a luma encoding process signal, using line segments forming a transform curve, each of which corresponds to a different one of sections obtained by partitioning the first pixel value space; and encodes an image, and in the performing of the LMCS, the circuitry determines the transform curve so that among boundary values in the second pixel value space, a first value obtained by dividing a boundary value by a base width defined according to a bit depth of the image is not equal to a second value obtained by dividing another boundary value by the base width.

公开(公告)号：US20220150599A1

公开(公告)日：2022-05-12

申请号：US17588936

申请日：2022-01-31

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Noritaka IGUCHI ,  Tadamasa TOMA ,  Hisaya KATOU

IPC: H04N21/643 ,  H04L69/22 ,  H04L61/5007 ,  H04N21/61 ,  H04N21/845 ,  H04N21/242 ,  H04N21/43 ,  H04L69/04 ,  H04N21/8547 ,  H04L69/28 ,  H04L69/32

Abstract: A transmission method includes: generating one or more transfer frames that each store one or more streams used for content transfer; and transmitting the one or more generated frames through broadcast, each of the one or more streams storing one or more second transfer units, each of the one or more second transfer units storing one or more first transfer units, and each of the one or more first transfer units storing one or more Internet Protocol (IP) packets. In at least one stream among the one or more streams, each of the first transfer units positioned at a head contains reference clock information indicating time used for reproduction of the content.

公开(公告)号：US20220150488A1

公开(公告)日：2022-05-12

申请号：US17580344

申请日：2022-01-20

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Chong Soon LIM ,  Hai Wei SUN ,  Sughosh Pavan SHASHIDHAR ,  Han Boon TEO ,  Ru Ling LIAO ,  Takahiro NISHI ,  Tadamasa TOMA

IPC: H04N19/119 ,  H04N19/176 ,  H04N19/50 ,  H04N19/60

Abstract: An encoder according to one aspect of the present disclosure encodes a block of an image, and includes a processor and memory connected to the processor. Using the memory, the processor partitions a block into a plurality of sub blocks and encodes a sub block included in the plurality of sub blocks in an encoding process including at least a transform process or a prediction process. The block is partitioned using a multiple partition including at least three odd-numbered child nodes and each of a width and a height of each of the plurality of sub blocks is a power of two.

公开(公告)号：US20220103843A1

公开(公告)日：2022-03-31

申请号：US17547608

申请日：2021-12-10

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Virginie DRUGEON ,  Tadamasa TOMA ,  Takahiro NISHI ,  Kiyofumi ABE ,  Yusuke KATO

IPC: H04N19/196 ,  H04N19/31 ,  H04N19/46 ,  H04N19/70

Abstract: An encoder includes memory and circuitry coupled to the memory. The circuitry, for each of temporal sub-layers for temporal scalability different from spatial scalability, stores first parameters into buffering period supplemental enhancement information (SEI) and encodes the first parameters. The first parameters present initial delays in timing to extract data from a coded picture buffer (CPB). The circuitry stores a second parameter into the buffering period SEI and encodes the second parameter. The second parameter indicates a total number of the temporal sub-layers. A value of the second parameter is equal to a value of a third parameter that is encoded into a sequence parameter set and indicates a total number of the temporal sub-layers.

公开(公告)号：US20220094949A1

公开(公告)日：2022-03-24

申请号：US17539348

申请日：2021-12-01

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi ABE ,  Takahiro NISHI ,  Tadamasa TOMA ,  Ryuichi KANOH ,  Chong Soon LIM ,  Ru Ling LIAO ,  Hai Wei SUN ,  Sughosh Pavan SHASHIDHAR ,  Han Boon TEO ,  Jing Ya LI

IPC: H04N19/176 ,  H04N19/105 ,  H04N19/52 ,  H04N19/70

Abstract: An encoder, includes: circuitry; and memory. Using the memory, the circuitry: in inter prediction for a current block, determines a base motion vector, and writes, in an encoded signal, a delta motion vector representing (i) one direction among a plurality of directions including a diagonal direction and (ii) a distance from the base motion vector; and encodes the current block using the delta motion vector and the base motion vector as a motion vector of the current block.