公开(公告)号：US07251011B2

公开(公告)日：2007-07-31

申请号：US11032215

申请日：2005-01-11

Applicant: Robert Walker ,  Bradley Caruk

Inventor： Robert Walker ,  Bradley Caruk

IPC: G03B25/00

CPC classification number: G09F19/22 ,  G09F2019/221

Abstract: A system displays a collection of stationary images as a motion picture to passengers traveling in a vehicle along a pathway. In a first embodiment, the vehicle moves at a known speed and known distance from the images. The images, placed in parallel along the walls of the pathway of the vehicle, are adapted in number, size, and spacing for a vehicle traveling at the known speed and at the known distance from images on one or both sides of the vehicle such as to maintain an approximately constant viewing rate and perceived size of the images. In an alternate configuration, a speed sensor monitors speed of the vehicle to determine the appropriate cycling rate of the images. In a preferred embodiment, the images themselves are cycled intermittently with a blank image while remaining steadily illuminated by an illumination system.

Abstract translation: 系统将沿车道行驶的乘客的静止图像集合显示为运动图像。 在第一实施例中，车辆以已知的速度和已知距离的图像移动。 沿着车辆的路径的壁平行放置的图像适用于以已知速度行驶的车辆的数量，尺寸和间隔，并且距离车辆的一侧或两侧上的图像已知距离，例如 以保持近似恒定的观看速率和感觉到的图像大小。 在替代配置中，速度传感器监测车辆的速度以确定图像的适当循环速率。 在优选实施例中，图像本身以空白图像间歇地循环，同时由照明系统稳定地照亮。

公开(公告)号：US20070115744A1

公开(公告)日：2007-05-24

申请号：US11623349

申请日：2007-01-16

Applicant: Robert Walker

Inventor： Robert Walker

IPC: G11C7/00

CPC classification number: G11C11/40626 ,  G11C7/1045 ,  G11C7/1072 ,  G11C11/406 ,  G11C2211/4061

Abstract: Data not stored in the DRAM array of a SDRAM module is read from the SDRAM module in a synchronous data transfer. The data transfer, referred to as register read command/operation, resembles a read command/operation directed to data stored in the DRAM array in timing and operation. The register read command is distinguished by a unique encoding of the SDRAM control signals and bank address bits. In one embodiment, the register read command comprises the same control signal states as a MSR or EMSR command, with the bank address set to a unique value, such as 2′b10. The register read command may read only a single datum, or may utilize the address bus to address a plurality of data not stored in the DRAM array. The register read operation may be a burst read, and the burst length may be defined in a variety of ways.

Abstract translation: 不存储在SDRAM模块的DRAM阵列中的数据在同步数据传输中从SDRAM模块读取。 被称为寄存器读命令/操作的数据传输类似于定时和操作中针对存储在DRAM阵列中的数据的读命令/操作。 寄存器读命令通过SDRAM控制信号和存储体地址位的唯一编码进行区分。 在一个实施例中，寄存器读取命令包括与MSR或EMSR命令相同的控制信号状态，其中存储体地址设置为唯一值，例如2'b10。 寄存器读取命令可以仅读取单个数据，或者可以利用地址总线来寻址未存储在DRAM阵列中的多个数据。 寄存器读取操作可以是突发读取，并且突发长度可以以各种方式定义。

公开(公告)号：US20070061157A1

公开(公告)日：2007-03-15

申请号：US11223065

申请日：2005-09-09

Applicant: Greg Fry ,  Robert Walker ,  Kim Jacksi ,  Richard Kohara ,  Kathleen Lucero

Inventor： Greg Fry ,  Robert Walker ,  Kim Jacksi ,  Richard Kohara ,  Kathleen Lucero

IPC: G06Q99/00

CPC classification number: G06Q10/06 ,  G06Q10/105 ,  G06Q40/00 ,  G06Q50/18

Abstract: Systems, methods, and machine-readable mediums are disclosed for managing assignment of obligations. In one embodiment, the method comprises receiving, at a compliance assurance system, an indication of a termination of employment of an individual and determining, with the compliance assurance system, the individual was assigned an obligation. A new responsible individual for the obligation is determined and the obligation is automatically assigned to the new responsible individual.

Abstract translation: 公开了用于管理义务分配的系统，方法和机器可读介质。 在一个实施例中，该方法包括在合规性保证系统处接收个人终止雇佣关系的指示，并且在合规保证系统中确定个人被赋予义务。 确定负责人的新责任人，并将义务自动分配给新的负责人。

公开(公告)号：US20070061156A1

公开(公告)日：2007-03-15

申请号：US11222528

申请日：2005-09-09

Applicant: Greg Fry ,  Robert Walker ,  Elaine Garley ,  Kathleen Lucero

Inventor： Greg Fry ,  Robert Walker ,  Elaine Garley ,  Kathleen Lucero

IPC: G06Q99/00

CPC classification number: G06Q99/00 ,  G06Q10/105 ,  G06Q40/00 ,  G06Q50/18

Abstract: In one embodiment, a compliance assurance system is disclosed which comprises a user interface, logic, and a data store. The user interface is configured to receive a request from a user to display at least a subset of legal obligations assigned to the user and to display the subset of legal obligations. The logic is configured to obtain the subset of legal obligations from the data store. The data store includes a plurality of legal obligations and a plurality of compliance plans, each associated with one of the legal obligations. The compliance plans specify at least one action to comply with the associated legal obligation.

Abstract translation: 在一个实施例中，公开了包括用户界面，逻辑和数据存储的合规性保证系统。 用户界面被配置为接收来自用户的请求，以显示分配给用户的至少一部分法定义务并显示法定义务的子集。 该逻辑被配置为从数据存储中获取法定义务的子集。 数据存储包括多个法律义务和多个合规计划，每个合规计划都与法律义务之一相关联。 合规计划规定至少采取一项行动来遵守相关的法律义务。

公开(公告)号：US20060294294A1

公开(公告)日：2006-12-28

申请号：US11165950

申请日：2005-06-23

Applicant: Robert Walker

Inventor： Robert Walker

IPC: G06F13/00

CPC classification number: G06F13/1668 ,  Y02D10/14

Abstract: Data not stored in the DRAM array of a SDRAM module, such as the output of a temperature sensor, are read from the SDRAM in a synchronous read cycle that is seamlessly interspersed with SDRAM read and write cycles directed to data in the DRAM array. Control information, including a non-DRAM indicator in the case of data not stored in a DRAM array, are maintained for all read cycles. Returned data stored in a DRAM array and data not stored in a DRAM array are buffered together. When extracting read data from the buffer, data not stored in a DRAM array are identified by the non-DRAM indicator and directed to circuits within the controller. When data not stored in the DRAM array indicates the temperature of the SDRAM die, the controller may adjust the refresh rate in response to the temperature.

公开(公告)号：US07111143B2

公开(公告)日：2006-09-19

申请号：US10747277

申请日：2003-12-30

Applicant: Robert Walker

Inventor： Robert Walker

IPC: G06F12/00

CPC classification number: G06F12/0879 ,  Y02D10/13

Abstract: A memory device, such as a DRAM, includes a memory array that is accessible for writing data in and reading data out, and a command decoder that decodes input control signals to produce commands for accessing the memory array. The set of commands for controlling access to the memory device can include a first memory access command for accessing the memory array using a first burst length, a second memory access command for accessing the memory array using a second burst length, and a terminate command that terminates a current memory access. The memory device can include a mode register that stores memory access parameters associated with accessing the memory array, including the burst lengths. Access to the memory array is switchable between the first burst length and the second burst length without altering the memory access parameters in the mode register.

Abstract translation: 诸如DRAM的存储器件包括可访问以用于将数据写入和读出数据的存储器阵列，以及解码输入控制信号以产生访问存储器阵列的命令的命令解码器。 用于控制对存储器件的访问的命令集可以包括用于使用第一突发长度访问存储器阵列的第一存储器访问命令，用于使用第二突发长度访问存储器阵列的第二存储器访问命令，以及终止命令， 终止当前内存访问。 存储器件可以包括模式寄存器，其存储与访问存储器阵列相关联的存储器访问参数，包括突发长度。 可以在第一突发长度和第二突发长度之间切换对存储器阵列的访问，而不改变模式寄存器中的存储器访问参数。

公开(公告)号：US20060145673A1

公开(公告)日：2006-07-06

申请号：US11028120

申请日：2005-01-03

Applicant: John Fogg ,  Robert Walker ,  Warren Schroeder

Inventor： John Fogg ,  Robert Walker ,  Warren Schroeder

IPC: G05F1/40 ,  G05F1/618

CPC classification number: G05F1/56 ,  H02J7/0029

Abstract: A voltage regulating circuit, such as a voltage regulator or battery charger, limits inrush current by buffering an associated supply input decoupling capacitor through a current path that is selectively configured to have a high impedance for startup charging of the decoupling capacitor at a low current, and a low impedance for normal operations of the circuit. Where the circuit uses multiple supply input connections for operation from two or more supply voltages, it may include buffering for each one of two or more supply input connections. It may further include a crossover switching control circuit that ensures make-before-break switching between supply input connections to avoid supply interruptions to the circuit during switchover.

Abstract translation: 诸如电压调节器或电池充电器的电压调节电路通过缓冲相关的电源输入去耦电容器来限制浪涌电流，该电流路径被选择性地配置为具有用于在低电流下去耦电容器的启动充电的高阻抗， 以及用于电路的正常操作的低阻抗。 在电路使用多个电源输入连接以从两个或多个电源电压进行操作的情况下，其可以包括两个或更多个电源输入连接中的每一个的缓冲。 它还可以包括一个交叉开关控制电路，其确保电源输入连接之间的断开前切换，以避免切换期间电路的电源中断。

公开(公告)号：US20060112250A1

公开(公告)日：2006-05-25

申请号：US10997140

申请日：2004-11-24

Applicant: Robert Walker

Inventor： Robert Walker

IPC: G06F13/00

CPC classification number: G06F13/1694 ,  G06F13/1689

Abstract: A memory system is disclosed in which the access speed may be adjusted. The memory system may include memory and a memory controller. The memory controller may be configured to generate a plurality of control signals to access the memory, and adjust the timing between the control signals to change the memory access speed as a function of a parameter related to the operation of the memory system.

Abstract translation: 公开了可以调整访问速度的存储器系统。 存储器系统可以包括存储器和存储器控制器。 存储器控制器可以被配置为产生多个控制信号以访问存储器，并且根据与存储器系统的操作相关的参数的函数来调整控制信号之间的定时以改变存储器访问速度。

公开(公告)号：US07031571B2

公开(公告)日：2006-04-18

申请号：US10803890

申请日：2004-03-19

Applicant: Stephen J. Mihailov ,  Dan Grobnic ,  Christopher Smelser ,  Robert Walker ,  Ping Lu ,  Huimin Ding ,  George Henderson ,  Xiaoli Dai

Inventor： Stephen J. Mihailov ,  Dan Grobnic ,  Christopher Smelser ,  Robert Walker ,  Ping Lu ,  Huimin Ding ,  George Henderson ,  Xiaoli Dai

IPC: G02B6/34

CPC classification number: G02B6/02138 ,  G02B5/1857 ,  G02B6/021 ,  G02B6/124

Abstract: A novel Bragg grating filter in optical waveguiding fiber with suppressed cladding mode coupling and method of producing same is disclosed. The novel grating structure is induced in both the core and the cladding of the optical fiber irrespective of the photosensitivity of the core or cladding to actinic radiation. Such core and cladding of the optical fiber need not be chemically doped to support the grating. The method incorporates an ultra short duration pulse laser source. Electromagnetic radiation provided from the laser propagates to a diffractive element positioned a specific distance to the target material such that the diffracted electromagnetic radiation forms a 2-beam interference pattern, the peaks of which are sufficiently intense to cause a change in index of refraction.

Abstract translation: 公开了一种具有抑制包层模耦合的光波导纤维中的新型布拉格光栅滤波器及其制造方法。 不管芯或包层对光化辐射的光敏性如何，在光纤的芯和包层中都引入新颖的光栅结构。 光纤的这种芯和包层不需要化学掺杂以支持光栅。 该方法结合了超短脉冲激光源。 从激光器提供的电磁辐射传播到与目标材料相距特定距离的衍射元件，使得衍射的电磁辐射形成2光束干涉图案，其峰值足够强以引起折射率的变化。

公开(公告)号：US20050288942A1

公开(公告)日：2005-12-29

申请号：US10876421

申请日：2004-06-25

Applicant: Benjamin Graboske ,  Robert Walker ,  Carrie Helbert

Inventor： Benjamin Graboske ,  Robert Walker ,  Carrie Helbert

IPC: G06Q40/00 ,  G06F17/60

CPC classification number: G06Q40/02 ,  G06Q30/0278 ,  G06Q40/00

Abstract: A method of obtaining valuations of property using multiple automated valuation models to receive the most accurate possible valuation quickly and at the lowest possible cost. An automated decision engine evaluates the accuracy and confidence score of the valuations given by various automated valuation models in a preselected order based upon their ability to provide accurate valuations in a particular geographic region. Additionally, the automated decision engine will provide a response to an individual's loan request to purchase property based on the relevant criteria and the accurate valuation it receives as a result of this method.

Abstract translation: 使用多个自动估值模型获得财产估值的方法，以尽可能快且最低的成本获得最准确的估值。 一个自动化决策引擎根据其在特定地理区域提供准确估值的能力，以预先选择的方式评估各种自动估值模型给出的估值的准确性和置信度。 此外，自动化决策引擎将根据相关标准以及由此方法获得的准确估值，为个人贷款购买物业的请求做出回应。