公开(公告)号：US10380306B2

公开(公告)日：2019-08-13

申请号：US15356817

申请日：2016-11-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shang-Chih Hsieh ,  Hui-Zhong Zhuang ,  Ting-Wei Chiang ,  Chun-Fu Chen ,  Hsiang-Jen Tseng

IPC: G06F17/50 ,  H03K19/02 ,  H01L27/02

Abstract: An integrated circuit designing system includes a non-transitory storage medium that is encoded with first and second sets of standard cell layouts that are configured for performing a selected function and which correspond to a specific manufacturing process. The manufacturing process is characterized by a nominal minimum pitch (T) for metal lines with each of the standard cell layouts being characterized by a cell height (H) that is a non-integral multiple of the nominal minimum pitch. The system also includes a hardware processor coupled to the storage medium for executing a set of instructions for generating an integrated circuit layout utilizing a combination of the first and second set of standard cell layouts and the nominal minimum pitch. The first and second sets of standard layouts are related in that each of the second set of standard cell layouts corresponds to a transformed version of a corresponding standard cell layout from the first set of standard cell layouts.

公开(公告)号：US10325900B2

公开(公告)日：2019-06-18

申请号：US16051241

申请日：2018-07-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chung-Te Lin ,  Ting-Wei Chiang ,  Hui-Zhong Zhuang ,  Pin-Dai Sue ,  Li-Chun Tien

IPC: H01L27/02 ,  G06F17/50 ,  H01L27/092 ,  H01L29/423 ,  H01L27/118

Abstract: A layout includes a plurality of cells and at least one dummy gate electrode continuously extends across the cells. Since the dummy gate electrode is electrically conductive, the dummy gate electrode can be utilized for interconnecting the cells. That is, some signals may travel through the dummy gate electrode rather than through a metal one line or a metal two line. Therefore, an amount of metal one lines and/or metal two lines for interconnecting the cells can be reduced.

公开(公告)号：US10296694B2

公开(公告)日：2019-05-21

申请号：US15707469

申请日：2017-09-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Ting-Wei Chiang ,  Hui-Zhong Zhuang ,  Li-Chun Tien

IPC: G06F17/50 ,  H01L27/02 ,  H01L27/092

Abstract: A method includes positioning a first set of conductive traces in a first direction, manufacturing a second set of conductive traces by a first mask pattern, and electrically coupling, by at least a first via, at least one conductive trace of the first set of conductive traces to at least one conductive trace of the second set of conductive traces. The first set of conductive traces is in a first layer of an integrated circuit. The second set of conductive traces is in a second direction different from the first direction. The second set of conductive traces is in a second layer of the integrated circuit. The second layer is different from the first layer. A conductive trace of the second set of conductive traces is part of a first dummy transistor.

公开(公告)号：US20190067290A1

公开(公告)日：2019-02-28

申请号：US15691974

申请日：2017-08-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Pochun Wang ,  Ting-Wei Chiang ,  Chih-Ming Lai ,  Hui-Zhong Zhuang ,  Jung-Chan Yang ,  Ru-Gun Liu ,  Shih-Ming Chang ,  Ya-Chi Chou ,  Yi-Hsiung Lin ,  Yu-Xuan Huang ,  Yu-Jung Chang ,  Guo-Huei Wu

IPC: H01L27/108 ,  H01L21/768 ,  H01L23/522 ,  H01L27/02 ,  H01L23/528

CPC classification number: H01L27/10823 ,  H01L21/76897 ,  H01L23/522 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/10808 ,  H01L27/10826 ,  H01L27/10829

Abstract: An integrated circuit includes a semiconductor substrate, an isolation region extending into, and overlying a bulk portion of, the semiconductor substrate, a buried conductive track comprising a portion in the isolation region, and a transistor having a source/drain region and a gate electrode. The source/drain region or the gate electrode is connected to the buried conductive track.

公开(公告)号：US20190067185A1

公开(公告)日：2019-02-28

申请号：US16174953

申请日：2018-10-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chung-Te Lin ,  Ting-Wei Chiang ,  Hui-Zhong Zhuang ,  Li-Chun Tien ,  Pin-Dai Sue

IPC: H01L23/522 ,  H01L27/02

Abstract: A device includes gates and a first conductive segment. A first distance is present between a first gate of the gates and the first conductive segment. A second distance is present between a second gate of the gates and the first conductive segment. The first distance is greater than the second distance.

公开(公告)号：US09767243B2

公开(公告)日：2017-09-19

申请号：US14464407

申请日：2014-08-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Ting-Wei Chiang ,  Hui-Zhong Zhuang ,  Li-Chun Tien

IPC: G06F17/50 ,  H01L27/02 ,  H01L27/092

CPC classification number: G06F17/5072 ,  H01L27/0207 ,  H01L27/092

Abstract: A system and method of layout design for an integrated circuit and integrated circuit, the method includes positioning all conductive traces of a first mask pattern, in a first direction, wherein the conductive traces of the first mask pattern are in a first conductive layer. The method also includes positioning all conductive traces of a second mask pattern, in the first direction, wherein the conductive traces of the second mask pattern are in the first conductive layer, and the second mask pattern is offset from the first mask pattern in a second direction different from the first direction.

公开(公告)号：US09536032B2

公开(公告)日：2017-01-03

申请号：US14554958

申请日：2014-11-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Ting-Wei Chiang ,  Li-Chun Tien ,  Hui-Zhong Zhuang ,  Zhe-Wei Jiang

IPC: G06F17/50 ,  H03K19/02 ,  H01L27/02

CPC classification number: G06F17/5072 ,  G06F17/5068 ,  H01L27/0207 ,  H03K19/02

Abstract: A method of forming a layout design for fabricating an integrated circuit is disclosed. The method includes identifying a line pattern of a first set of grid lines with respect to a second set of grid lines within a region of the layout design; and placing a k-th standard cell layout of the K standard cell layouts at the region of the layout design if the line pattern is determined to match a k-th predetermined line pattern of K predetermined line patterns. K is an integer equal to or greater than two, and k is an order index ranging from 1 to K. The region of the layout design is sized to fit one of K different standard cell layouts corresponding to a same standard cell functionality.

Abstract translation: 公开了一种形成用于制造集成电路的布局设计的方法。 该方法包括在布局设计的区域内相对于第二组网格线识别第一组网格线的线图案; 以及如果所述线图案被确定为匹配K个预定线图案的第k个预定线图案，则将所述K个标准单元布局的第k个标准单元布局放置在所述布局设计的区域。 K是等于或大于2的整数，k是范围从1到K的订单索引。布局设计的区域的大小适合于对应于相同标准单元功能的K个不同标准单元布局中的一个。

公开(公告)号：US09317646B2

公开(公告)日：2016-04-19

申请号：US14826553

申请日：2015-08-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Lee-Chung Lu ,  Li-Chun Tien ,  Hui-Zhong Zhuang ,  Chang-Yu Wu

IPC: G06F17/50 ,  H01L27/092 ,  H01L27/02

CPC classification number: G06F17/5072 ,  H01L27/0207 ,  H01L27/092

Abstract: A set of masks corresponds to an integrated circuit layout. The integrated circuit layout includes a first cell having a first transistor region and a second transistor region, and a second cell having a third transistor region and a fourth transistor region. The first cell and the second cell adjoin each other at side cell boundaries thereof, the first transistor region and the third transistor region are formed in a first continuous active region, and the second transistor region and the fourth transistor region are formed in a second continuous active region. The set of masks is formed based on the integrated circuit layout.

Abstract translation: 一组掩模对应于集成电路布局。 集成电路布局包括具有第一晶体管区和第二晶体管区的第一单元，以及具有第三晶体管区和第四晶体管区的第二单元。 第一单元和第二单元在其单元边界彼此相邻，第一晶体管区和第三晶体管区形成在第一连续有源区中，并且第二晶体管区和第四晶体管区形成为第二连续 活跃区域。 基于集成电路布局形成掩模组。

公开(公告)号：US09123565B2

公开(公告)日：2015-09-01

申请号：US13779104

申请日：2013-02-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Lee-Chung Lu ,  Li-Chun Tien ,  Hui-Zhong Zhuang ,  Chang-Yu Wu

IPC: H01L27/088 ,  H01L27/092 ,  H01L27/02

CPC classification number: G06F17/5072 ,  H01L27/0207 ,  H01L27/092

Abstract: An integrated circuit layout that includes a first standard cell having a first transistor region and a second transistor region; a second standard cell having a third transistor region and a fourth transistor region. The first and second standard cells adjoin each other at side boundaries thereof and the first transistor region and the third transistor region are formed in a first continuous active region, and the second transistor region and the fourth transistor region are formed in a second continuous region.

Abstract translation: 一种集成电路布局，包括具有第一晶体管区域和第二晶体管区域的第一标准单元; 具有第三晶体管区域和第四晶体管区域的第二标准单元。 第一和第二标准单元在其边界彼此相邻，并且第一晶体管区域和第三晶体管区域形成在第一连续有源区中，并且第二晶体管区域和第四晶体管区域形成在第二连续区域中。

公开(公告)号：US20150171005A1

公开(公告)日：2015-06-18

申请号：US14104730

申请日：2013-12-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Wei-Yu Chen ,  Li-Chun Tien ,  Hui-Zhong Zhuang ,  Ting-Wei Chiang ,  Hsiang-Jen Tseng

IPC: H01L23/522 ,  H01L23/528 ,  G06F17/50

CPC classification number: H01L23/5226 ,  G06F17/5077 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit layout includes a first metal line, a second metal line, at least one first conductive via and a first conductive segment. The first metal line is formed along a first direction. The at least one first conductive via is disposed over the first metal line. The second metal line is disposed over at least one first conductive via and is in parallel with the first metal line. The first conductive segment is formed on one end of the second metal line.

Abstract translation: 集成电路布局包括第一金属线，第二金属线，至少一个第一导电通孔和第一导电段。 第一金属线沿第一方向形成。 所述至少一个第一导电通孔设置在所述第一金属线上。 第二金属线设置在至少一个第一导电通孔上并与第一金属线并联。 第一导电段形成在第二金属线的一端上。