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公开(公告)号：US4677619A
公开(公告)日：1987-06-30
申请号：US657000
申请日：1984-10-02
Applicant: Masahisa Kawai
Inventor： Masahisa Kawai
CPC classification number: G01R29/033 , G01R23/15 , H04L1/241 , H04L1/242
Abstract: A supervisory system is disclosed for a digital radio transmission line connected between a transmitter part and a receiver. The receiver produces error pulses from a portion on the transmitted message used for error rate detection sent from the transmitter. Transmission line quality is estimated in accordance with the variation of time intervals between each two successive error pulses.
Abstract translation: 公开了一种连接在发射机部分和接收机之间的数字无线电传输线路的监控系统。 接收器从用于发射机发送的错误率检测的发送消息的一部分产生误差脉冲。 根据每两个连续的错误脉冲之间的时间间隔的变化来估计传输线质量。
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132.发明授权
公开(公告)号：US4592044A
公开(公告)日：1986-05-27
申请号：US613049
申请日：1984-05-22
Applicant: James J. Ferenc
Inventor： James J. Ferenc
Abstract: Apparatus and method are disclosed for checking the time slot data word integrity of data communications in a time multiplexed communication system. A predetermined control bit of each data word of a data frame is alternately switched from its normal control bit function to a bit of a pseudo random sequence (PRS) for time slot data word integrity checking. During alternate data frames a checking circuit compares the predetermined bit of received consecutive data words against consecutive bits of a reference PRS and outputs a time slot cross connect error signal when a difference occurs.
Abstract translation: 公开了用于检查时分复用通信系统中数据通信的时隙数据字完整性的装置和方法。 将数据帧的每个数据字的预定控制位从其正常控制位功能交替地切换到用于时隙数据字完整性检查的伪随机序列（PRS）的位。 在替代数据帧期间，检查电路将接收到的连续数据字的预定位与参考PRS的连续位进行比较，并且当发生差异时输出时隙交叉错误信号。
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133.发明授权
公开(公告)号：US4587653A
公开(公告)日：1986-05-06
申请号：US537909
申请日：1983-09-30
Applicant: Charles R. Hogge, Jr.
Inventor： Charles R. Hogge, Jr.
CPC classification number: H04L1/241
Abstract: A circuit for generating pseudoerrors when the value of a received digital bit signal enters a pseudoerror region, as may be employed in the control loop of an adaptive system. The circuit includes its own feedback to control the boundaries of the pseudoerror region so that the rate of pseudoerror generation lies within a useful range.
Abstract translation: 当接收到的数字位信号的值进入伪误差区域时，用于产生伪误差的电路，如可以在自适应系统的控制环路中所采用的那样。 该电路包括其自己的反馈来控制伪错误区域的边界，使得伪错误产生的速率在有用的范围内。
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134.发明授权
公开(公告)号：US4367550A
公开(公告)日：1983-01-04
申请号：US249238
申请日：1981-03-30
Applicant: Egon Douverne
Inventor： Egon Douverne
CPC classification number: H04L1/241
Abstract: A method for monitoring the bit error rate of digital signals according to the pseudo error rate technique which includes effecting an optimal regeneration of the signal elements in a main signal path by sampling each signal element in that path, and effecting a degraded regeneration of the signal elements in a secondary path. Regeneration in the secondary signal path is carried out by sampling each signal element twice to determine its value, once a fraction of half the element period before the midpoint of the element period and once the same fraction of half the element period after the midpoint of the element period, the two sampling moments being rigidly coupled together in time, comparing the result of each of the two samplings of one element in the secondary signal path with the result of the sampling of the same element in the main signal path, and utilizing the number of disagreements occurring over a given time interval as a measure for the bit error rate in the main signal path.
Abstract translation: 一种用于根据伪错误率技术监视数字信号的误码率的方法，其包括通过对该信道中的每个信号元素进行采样来实现主信号路径中的信号元件的最佳再生，并且实现信号的劣化再生 次要路径中的元素。 次要信号路径中的再生是通过对每个信号元素进行两次采样来确定其值，一次是在元素周期的中点之前的元素周期的一半的一半，并且在元素周期的中点之后的元素周期的一半的相同分数 将两个采样时刻在时间上刚性地耦合在一起，将次级信号路径中的一个元件的两个采样的结果与主信号路径中的相同元件的采样结果进行比较，并利用 在给定时间间隔内发生的不一致的数量作为主信号路径中的误码率的度量。
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135.发明授权Method for testing a digital data transmission line between two modems and a device for the application of said method 失效用于测试两个调制解调器之间的数字数据传输线和用于所述方法的应用的设备的方法
公开(公告)号：US4351059A
公开(公告)日：1982-09-21
申请号：US187771
申请日：1980-09-16
Applicant: Michel Gregoire , Jean C. Vuillemin
Inventor： Michel Gregoire , Jean C. Vuillemin
Abstract: A method for testing a digital data transmission line connected between two modems, including the steps of transmitting a test message from the first modem to the second modem, comparing the received message with the standard test message to determine errors, transmitting a test message back to the first modem along with the error message determined from comparing the received test message with the standard test message at the first modem. The error signal transmitted to the first modem and the error detected there is interpreted to determine the error in the transmission.
Abstract translation: 一种用于测试连接在两个调制解调器之间的数字数据传输线的方法，包括以下步骤：将测试消息从第一调制解调器发送到第二调制解调器，将接收到的消息与标准测试消息进行比较以确定错误，将测试消息发送回 第一调制解调器以及通过将接收到的测试消息与第一调制解调器上的标准测试消息进行比较而确定的错误消息。 发送到第一调制解调器的错误信号和在那里检测到的错误被解释为确定传输中的错误。
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Patent Agency Ranking136.发明授权Method for generating a pseudo-signal in an error rate supervisory unit and circuit for carrying out the same 失效用于在错误率监控单元中产生伪信号的方法和用于执行该伪信号的电路
公开(公告)号：US4247938A
公开(公告)日：1981-01-27
申请号：US040408
申请日：1979-05-18
Applicant: Hiroshi Kurihara , Tadayoshi Katoh , Sadao Takenaka
Inventor： Hiroshi Kurihara , Tadayoshi Katoh , Sadao Takenaka
CPC classification number: H04L1/241
Abstract: A method and circuit for generating a pseudo-error signal comprising a demodulator circuit for demodulating an input signal; a first discriminator circuit for regenerating a first digital data signal by discriminating the output of the demodulator circuit; a noise extracting means for extracting a noise component from the input signal; an adding circuit for adding the output of the noise extracting means and the output of the demodulator circuit; a second discriminator circuit for regenerating a second digital data signal by discriminating the output of the adding circuit, and; an exclusive OR circuit for recognizing whether or not the first digital data signal coincides with the second digital data signal.
Abstract translation: 一种用于产生伪误差信号的方法和电路，包括用于解调输入信号的解调器电路; 用于通过识别解调器电路的输出来再生第一数字数据信号的第一鉴别器电路; 噪声提取装置，用于从输入信号中提取噪声分量; 用于将噪声提取装置的输出和解调器电路的输出相加的加法电路; 第二鉴别器电路，用于通过识别加法电路的输出来再生第二数字数据信号; 用于识别第一数字数据信号是否与第二数字数据信号一致的异或电路。
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公开(公告)号：US4143354A
公开(公告)日：1979-03-06
申请号：US794512
申请日：1977-05-06
Applicant: Alan G. Stoddart
Inventor： Alan G. Stoddart
Abstract: A method of error detection in a digital system in which at least one digit in every n (where n is an integer greater than two) is omitted from use as the "particular digit" in the comparison of succeeding particular digits in a received pattern with the combination in accordance with a predetermined function of at least two digits preceding the particular digit in question by a particular spacing. The pattern is a pseudo-random binary sequence of maximal length and every third digit is taken as the particular digit. Every digit forms part of a comparison whether as "particular digit" or as one of said "at least two digits preceding". Shift registers, means to divide digits between the shift registers, and modulo -2 adders are used to carry out the method.
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138.发明授权
公开(公告)号：US4091240A
公开(公告)日：1978-05-23
申请号：US777739
申请日：1977-03-15
Applicant: Gilbert P. Lainey , Daniel R. Duponteil
Inventor： Gilbert P. Lainey , Daniel R. Duponteil
CPC classification number: H04L1/241
Abstract: A bit error rate performance monitor unit for use in digital transmission links in which the signal input is equally divided between two demodulators of which one is disturbed, the combined output of said modulators being fed to an adder, the output of said adder being connected to a counter for continuously counting the bit error rate of the link.
Abstract translation: 一种用于数字传输链路的误码率性能监视单元，其中信号输入在其中被干扰的两个解调器之间被等分，所述调制器的组合输出被馈送到加法器，所述加法器的输出连接到 用于连续计数链路误码率的计数器。
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139.发明授权
公开(公告)号：US4091239A
公开(公告)日：1978-05-23
申请号：US777740
申请日：1977-03-15
Applicant: Gilbert P. Lainey , Jean-Claude A. Imbeaux
Inventor： Gilbert P. Lainey , Jean-Claude A. Imbeaux
CPC classification number: H04L1/241
Abstract: A bit error performance monitor in which the input signal is equally shared by two substantially identical monitors whose outputs in turn are connected to an adder. The output of the adder passes through a divider-by-2 to a counter.
Abstract translation: 一个误码性能监视器，其中输入信号被两个基本上相同的监视器共享，其输出又连接到加法器。 加法器的输出通过分频器2到计数器。
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公开(公告)号：US3914740A
公开(公告)日：1975-10-21
申请号：US39408873
申请日：1973-09-04
Applicant: NORTHERN ELECTRIC CO
Inventor： HAN SWAN BING
Abstract: An error detector for a pseudo-random sequence of digits which automatically provides a true error count regardless of the density and pattern of the received errors. The detector first compares the incoming sequence with a replicated sequence to derive indicated error digits. A corrector then compares the sequence arrangement of all indicated error digits to derive a further sequence of only true error digits. Both the detector and corrector will automatically resynchronize if synchronization is lost with only a few false errors being recorded during the interval.
Abstract translation: 用于伪随机数字序列的误差检测器，其自动提供真实误差计数，而不管接收到的误差的密度和模式如何。 检测器首先将输入序列与复制序列进行比较，以得出指示的错误数字。 然后，校正器比较所有指示的错误数字的序列排列，以导出仅真实错误数字的另外的序列。 如果同步丢失，检测器和校正器将自动重新同步，在间隔期间只记录几个假错误。
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