公开(公告)号：US12236867B2

公开(公告)日：2025-02-25

申请号：US17789174

申请日：2021-09-30

Applicant: BOE Technology Group Co., Ltd.

Inventor： Lujiang Huangfu ,  Li Wang ,  Jianchao Zhu ,  Libin Liu ,  Yu Feng

IPC: G09G3/3233

Abstract: A pixel driving circuit is provided. The pixel driving circuit includes a storage capacitor (Cst) having a first capacitor electrode (Ce1) and a second capacitor electrode (Ce2); a driving transistor (Td) configured to generate a driving current; and a switch (SW) configured to control connection or disconnection between a gate electrode of the driving transistor (Td) and the first capacitor electrode (Ce1).

公开(公告)号：US12223908B2

公开(公告)日：2025-02-11

申请号：US18262598

申请日：2022-08-24

Applicant: BOE Technology Group Co., Ltd.

Inventor： Zhenzhen Shan ,  Libin Liu ,  Jiangnan Lu ,  Shiming Shi

IPC: G09G3/3258 ,  G09G3/32 ,  G09G3/3233 ,  G09G3/3266 ,  G11C19/28 ,  H01L27/12 ,  H01L21/77

Abstract: A display substrate includes a pixel driving circuit, which includes a driving circuit, a storage circuit and a reset circuit. The reset circuit is electrically connected to a first terminal of the driving circuit. The driving circuit is used to conduct a path between the first terminal and a second terminal of the driving circuit under the control of a potential at its control terminal. The storage circuit is electrically connected to the control terminal of the driving circuit. The reset circuit includes a first capacitor. The storage circuit includes a second capacitor. An area of an overlap between orthographic projections of a first electrode plate and a second electrode plate of the first capacitor on the base substrate is smaller than that of the second capacitor on the base substrate.

公开(公告)号：US12205540B2

公开(公告)日：2025-01-21

申请号：US17764395

申请日：2021-03-18

Applicant: BOE Technology Group Co., Ltd.

Inventor： Jiangnan Lu ,  Guangliang Shang ,  Xinshe Yin ,  Libin Liu ,  Jianchao Zhu ,  Hao Zhang ,  Ke Feng

IPC: G09G3/3233 ,  G09G3/3258 ,  G09G3/3266 ,  G09G3/36 ,  G11C19/28

Abstract: A shift register unit, a driving method thereof, a gate driving circuit and a display panel are provided. The shift register unit includes an input circuit, a reset circuit, a first output circuit and a second output circuit; the input circuit is configured to control a level of a first node in response to a first input signal; the reset circuit is configured to reset the first node in response to a reset signal; the first output circuit is configured to output a shift signal under control of the level of the first node; and the second output circuit is configured to, in a first phase, under control of the level of the first node, output a plurality of sub-pulses at the first output terminal as a first output signal in a case where the shift output terminal outputs a first level of the shift signal.

公开(公告)号：US20250006133A1

公开(公告)日：2025-01-02

申请号：US18264043

申请日：2022-11-30

Applicant: BOE Technology Group Co., Ltd.

Inventor： Yu Feng ,  Libin Liu ,  Shiming Shi

IPC: G09G3/3266 ,  G09G3/32

Abstract: A driving circuit is provided. The driving circuit includes one or more scan circuits; wherein the one or more scan circuits comprise a first scan circuit; wherein the first scan circuit comprises a plurality of first scan sub-circuits; and at least two first scan sub-circuits of the plurality of first scan sub-circuits are configured to drive two display sub-areas of a plurality of display sub-areas of a display area with two different driving frequencies in at least one frame of image, respectively.

公开(公告)号：US12131698B2

公开(公告)日：2024-10-29

申请号：US17638720

申请日：2021-02-18

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Yuhan Qian ,  Libin Liu

IPC: H01L27/14 ,  G09G3/3233 ,  H10K59/131 ,  H10K71/00 ,  H10K59/12

CPC classification number: G09G3/3233 ,  H10K59/131 ,  H10K71/00 ,  G09G2300/0426 ,  G09G2300/0819 ,  G09G2300/0842 ,  H10K59/1201

Abstract: A pixel driving circuit includes a first thin film transistor having a double-gate structure, a conductive layer and a second thin film transistor. The first thin film transistor includes a first active layer. The first active layer includes a first and second semiconductor portions and a conductor portion located therebetween. The conductor portion has a first doping concentration. The conductive layer is at least partially opposite to the conductor portion, so that the conductive layer and the conductor portion form a capacitor. The conductive layer is configured to electrically connect to an initial voltage terminal. The second thin film transistor includes a second active layer and a first gate. A portion of the second active layer directly opposite to the first gate has a second doping concentration, and the second doping concentration is lower than the first doping concentration.

公开(公告)号：US12108643B2

公开(公告)日：2024-10-01

申请号：US17953941

申请日：2022-09-27

Applicant: BOE Technology Group Co., Ltd.

Inventor： Jiangnan Lu ,  Guangliang Shang ,  Can Zheng ,  Yu Feng ,  Libin Liu ,  Jie Zhang ,  Mei Li

IPC: H10K59/131 ,  G09G3/3208 ,  H10K59/121

CPC classification number: H10K59/131 ,  H10K59/121 ,  G09G3/3208 ,  G09G2320/0209 ,  G09G2320/0233

Abstract: Provided is a display substrate, the display substrate is provided with a display area and a peripheral area around the display area, and includes: a source/drain layer, a planarization layer and an anode layer which are laminated in sequence, wherein in the peripheral area, the source/drain layer includes at least one pair of first signal lines including a signal line of a gate circuit and the anode layer includes a common power line provided with vent holes; and overlapping areas between two first signal lines in any pair of the first signal lines and a projection pattern of the vent hole are equal, the projection pattern of the vent hole being a pattern of an orthographic projection of the vent hole in the common power line onto the source/drain layer. A display panel and a display device are also provided.

公开(公告)号：US12052901B2

公开(公告)日：2024-07-30

申请号：US17310325

申请日：2021-03-15

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Libin Liu ,  Mei Li ,  Shiming Shi ,  Li Wang

IPC: H10K59/35 ,  H10K50/80 ,  H10K59/122 ,  H10K59/131 ,  H10K71/00 ,  H10K59/12

CPC classification number: H10K59/353 ,  H10K50/80 ,  H10K59/122 ,  H10K59/131 ,  H10K59/352 ,  H10K71/00 ,  H10K59/1201

Abstract: The present disclosure provides a display substrate, a manufacturing method thereof, and a display device. The display substrate includes a display area and a non-display area located at a periphery of the display area, wherein the display area includes a plurality of pixel opening areas and a pixel spacing area located between the pixel opening areas; the display substrate further includes: a first electrode, wherein at least part of the first electrode is located in the pixel spacing area, an orthographic projection of the first electrode on a substrate of the display substrate does not overlap an orthographic projection of the pixel opening area on the substrate; and a second electrode electrically connected to the first electrode and located in the non-display area.

公开(公告)号：US11937465B2

公开(公告)日：2024-03-19

申请号：US17630908

申请日：2021-03-11

Applicant: BOE Technology Group Co., Ltd.

Inventor： Libin Liu ,  Jiangnan Lu

IPC: H10K59/124 ,  G09G3/3233

CPC classification number: H10K59/124 ,  G09G3/3233 ,  G09G2300/0426 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2300/0861 ,  G09G2310/08 ,  G09G2320/0233

Abstract: Embodiments of the present disclosure relate to the field of display technology, and in particular, to an array substrate, a display panel and a display device thereof. The array substrate includes a substrate and a plurality of sub-pixels on the substrate. Each sub-pixel includes a pixel circuit. The pixel circuit includes a plurality of transistors. The plurality of transistors includes at least one oxide transistor. The array substrate further includes: an oxide semiconductor layer on the substrate, the oxide semiconductor layer comprising a channel region of the oxide transistor; a first planarization layer on the substrate and covering at least a portion of the oxide semiconductor layer; a barrier part on the side of the first planarization layer away from the substrate.

公开(公告)号：US11875748B2

公开(公告)日：2024-01-16

申请号：US17433668

申请日：2021-02-24

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Guangliang Shang ,  Tian Dong ,  Xinshe Yin ,  Mei Li ,  Libin Liu ,  Shiming Shi

IPC: G11C19/28 ,  G09G3/3266 ,  G09G3/3233 ,  G09G3/20

CPC classification number: G09G3/3266 ,  G11C19/28 ,  G09G3/20 ,  G09G3/3233 ,  G09G2300/0426 ,  G09G2310/0286 ,  G09G2320/0247 ,  G09G2330/021

Abstract: Provided are a gate driving circuit, a display substrate, a display device and a gate driving method, the gate driving circuit includes: a frequency doubling control circuit and an effective output circuit including first shift registers, the first shift register at the first stage has a first signal input terminal coupled with an output control signal line and a second signal input terminal coupled with the frequency doubling control circuit; the frequency doubling control circuit is coupled to the output control signal line, for providing a frequency doubling control signal thereto after a preset time period from the receipt of the output control signal in response to an output control signal from the output control signal line; the first shift register at the first stage outputs a scanning signal in response to the output control signal and a scanning signal in response to the frequency doubling control signal.

公开(公告)号：US11875747B2

公开(公告)日：2024-01-16

申请号：US17793841

申请日：2021-05-17

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Lujiang Huangfu ,  Li Wang ,  Can Zheng ,  Tian Dong ,  Libin Liu

IPC: G09G3/3258 ,  G09G3/3233

CPC classification number: G09G3/3258 ,  G09G3/3233 ,  G09G2300/0819 ,  G09G2300/0852 ,  G09G2310/0251 ,  G09G2310/0262 ,  G09G2310/061 ,  G09G2320/0214 ,  G09G2320/0233 ,  G09G2320/0238 ,  G09G2320/0247 ,  G09G2320/043

Abstract: A pixel driving circuit includes: an energy storage sub-circuit, a reset sub-circuit, a compensation sub-circuit, a driving sub-circuit, and a current leakage suppression sub-circuit. The energy storage sub-circuit is coupled to a first node and a second node. The reset sub-circuit is coupled to the second node, a first scan timing signal terminal, and an initialization signal terminal. The compensation sub-circuit is coupled to the second node, a third node, and a second scan timing signal terminal. The driving sub-circuit is coupled to the second node, the third node, and a first voltage signal terminal. The current leakage suppression sub-circuit is coupled to the energy storage sub-circuit, the reset sub-circuit, and the compensation sub-circuit. The current leakage suppression sub-circuit is configured to suppress current leakage of the energy storage sub-circuit in a process of generating and transmitting the driving signal by the driving sub-circuit.