公开(公告)号：US20080086673A1

公开(公告)日：2008-04-10

申请号：US11704068

申请日：2007-02-08

申请人： Ba-Zhong Shen ,  Tak K. Lee

发明人： Ba-Zhong Shen ,  Tak K. Lee

IPC分类号： H03M13/00

CPC分类号： H03M13/2775 ,  H03M13/2957 ,  H03M13/2978 ,  H03M13/6525 ,  H03M13/6561

摘要： General and algebraic-constructed contention-free memory mapping for parallel turbo decoding with algebraic interleave ARP (almost regular permutation) of all possible sizes. A novel means is presented in which contention-free memory mapping is truly achieved in the context of performing parallel decoding of a turbo coded signal. A novel means of performing the contention-free memory mapping is provided to ensure that any one turbo decoder (of a group of parallel arranged turbo decoders) accesses only memory (of a group of parallel arranged memories) at any given time. In doing so, access conflicts between the turbo decoders and the memories are avoided.

摘要翻译： 通用和代数构造的无竞争存储器映射，用于具有所有可能大小的代数交织ARP（几乎规则排列）的并行turbo解码。 提出了一种新颖的手段，其中在执行turbo编码信号的并行解码的上下文中真正地实现了无竞争存储器映射。 提供执行无竞争存储器映射的新颖方式，以确保任何一个turbo解码器（一组并行布置的turbo解码器）在任何给定时间仅访问存储器（一组并行布置的存储器）。 在这样做时，避免turbo解码器和存储器之间的访问冲突。

公开(公告)号：US08640011B2

公开(公告)日：2014-01-28

申请号：US13559788

申请日：2012-07-27

申请人： Ba-Zhong Shen ,  Tak K. Lee

发明人： Ba-Zhong Shen ,  Tak K. Lee

IPC分类号： H03M13/11

CPC分类号： H03M13/09 ,  H04L1/0057 ,  H04L1/0066

摘要： Single CRC polynomial for both turbo code block CRC and transport block CRC. Rather than employing multiple and different generation polynomials for generating CRC fields for different levels within a coded signal, a single CRC polynomial is employed for the various levels. Effective error correction capability is achieved with minimal hardware requirement by using a single CRC polynomial for various layers of CRC encoding. Such CRC encoding can be implemented within any of a wide variety of communication devices that may be implemented within a wide variety of communication systems (e.g., a satellite communication system, a wireless communication system, a wired communication system, and a fiber-optic communication system, etc.). In addition, a single CRC check can be employed within a receiver (or transceiver) type communication device for each of the various layers of CRC of a received signal.

摘要翻译： 用于turbo码块CRC和传输块CRC的单个CRC多项式。 不是采用多个不同的生成多项式来生成用于编码信号内的不同级别的CRC字段，而是针对各种级别使用单个CRC多项式。 通过对CRC编码的各个层使用单个CRC多项式，以最小的硬件要求实现了有效的纠错能力。 这种CRC编码可以在可以在各种各样的通信系统（例如，卫星通信系统，无线通信系统，有线通信系统和光纤通信）中实现的各种通信设备中的任何一种内实现 系统等）。 此外，对于接收信号的CRC的各个层中的每一个，可以在接收机（或收发器）类型通信设备内采用单个CRC校验。

公开(公告)号：US08473829B2

公开(公告)日：2013-06-25

申请号：US12941178

申请日：2010-11-08

申请人： Tak K. Lee ,  Ba-Zhong Shen

发明人： Tak K. Lee ,  Ba-Zhong Shen

IPC分类号： H03M13/00

CPC分类号： H03M13/2771 ,  H03M13/276 ,  H03M13/2957 ,  H03M13/6561 ,  H04L1/005 ,  H04L1/0066

摘要： Address generation for contention-free memory mappings of turbo codes with ARP (almost regular permutation) interleaves. Anticipatory address generation is employed using an index function , that is based on an address mapping , which corresponds to an interleave inverse order of decoding processing (π−1). In accordance with parallel turbo decoding processing, instead of performing the natural order phase decoding processing by accessing data elements from memory bank locations sequentially, the accessing of addresses is performed based on the index function , that is based on an mapping and the interleave (π) employed within the turbo coding. In other words, the accessing data elements from memory bank locations is not sequential for natural order phase decoding processing. The index function also allows for the interleave (π) order phase decoding processing to be performed by accessing data elements from memory bank locations sequentially.

摘要翻译： 具有ARP（几乎规则排列）交织的turbo码的无竞争内存映射的地址生成。 使用基于地址映射的索引函数来采用预期地址生成，该地址映射对应于解码处理（pi-1）的交织逆序。 根据并行turbo解码处理，代替通过依次从存储体单元访问数据元素来执行自然次序相位解码处理，基于索引函数执行地址的访问，该索引函数是基于映射和交织（pi ）。 换句话说，来自存储体位置的访问数据元素对于自然顺序相位解码处理不是顺序的。 索引函数还允许通过从存储体单元顺序访问数据元素来执行交织（pi）阶相位解码处理。

公开(公告)号：US20120054578A1

公开(公告)日：2012-03-01

申请号：US13293231

申请日：2011-11-10

申请人： Ba-Zhong Shen ,  Tak K. Lee

发明人： Ba-Zhong Shen ,  Tak K. Lee

IPC分类号： H03M13/29 ,  G06F11/10

CPC分类号： H03M13/2957 ,  H03M13/2757 ,  H03M13/2785 ,  H03M13/3972 ,  H03M13/6566 ,  H04L1/0071

摘要： Formulaic flexible collision-free memory accessing for parallel turbo decoding with quadratic polynomial permutation (QPP) interleave. A means is presented by which any desired number of parallel implemented turbo decoding processors can be employed to perform turbo decoding that has been performed using a QPP interleave. This approach is presented to allow an arbitrarily selected number (M) of decoding processors (e.g., a plurality of parallel implemented turbo decoders) to perform decoding of a turbo coded signal while still using a selected embodiment of a QPP interleave. In addition, a collision-free memory mapping, (MOD,C,W) provides more freedom for selecting the particular quadratic polynomial permutation (QPP) interleave (π) that satisfies a parallel turbo decoding implementation with any desired number of parallel implemented turbo decoding processors. This memory mapping allows collision-free reading and writing of updated information (as updated using parallel implemented turbo decoder) into memory banks.

摘要翻译： 具有二次多项式置换（QPP）交错的并行涡轮解码的公式灵活无冲突存储器存取。 提出了一种可以使用任何期望数量的并行实施的turbo解码处理器来执行已经使用QPP交织进行的turbo解码的装置。 呈现该方法以允许任意选择的数量（M）的解码处理器（例如，多个并行实现的turbo解码器）在仍然使用QPP交织的所选实施例的情况下执行turbo编码信号的解码。 此外，无冲突存储器映射（MOD，C，W）提供了更多的自由度，用于选择满足具有任何所需数量的并行实现的turbo的并行turbo解码实现的特定二次多项式置换（QPP）交织（＆pgr） 解码处理器。 该存储器映射允许将更新的信息（使用并行实现的turbo解码器更新）的无冲突读写写入存储体。

公开(公告)号：US08069400B2

公开(公告)日：2011-11-29

申请号：US12132971

申请日：2008-06-04

申请人： Ba-Zhong Shen ,  Tak K. Lee

发明人： Ba-Zhong Shen ,  Tak K. Lee

IPC分类号： H03M13/03

CPC分类号： H04L1/0066 ,  H04L1/005 ,  H04L1/0069

摘要： Optimal circular buffer rate matching for turbo code. An offset index, δ, of 3 and a skipping index, σ, of 3 is employed in accordance with circular buffer rate matching. This allows less puncturing of information bits and more puncturing of redundancy/parity bits (e.g., which can provide for a higher rate). Multiple turbo codes may be generated from a mother code such that each generated turbo code can be employed to encode information bits. For example, a first turbo coded signal can be generated using a first turbo code generated from the mother code, and a second turbo coded signal can be generated using a second turbo code generated from the mother code. Any of these turbo coded signal can be decoded using parallel decoding processing or a single turbo decoder (when each turbo coded signal undergoes processing to transform it back to the mother code format).

摘要翻译： turbo码的最优循环缓冲率匹配。 根据循环缓冲速率匹配采用3的偏移索引δ和3的跳过索引＆sgr。 这允许更少地删除信息比特，并且更多地删除冗余/奇偶校验位（例如，其可以提供更高的速率）。 可以从母码生成多个turbo码，使得可以采用每个生成的turbo码对信息比特进行编码。 例如，可以使用从母码产生的第一turbo码生成第一turbo编码信号，并且可以使用从母码产生的第二turbo码生成第二turbo编码信号。 可以使用并行解码处理或单个turbo解码器来解码这些turbo编码信号中的任何一个（当每个turbo编码信号经历处理以将其转换回母码格式时）。

公开(公告)号：US08069387B2

公开(公告)日：2011-11-29

申请号：US12111863

申请日：2008-04-29

申请人： Ba-Zhong Shen ,  Tak K. Lee

发明人： Ba-Zhong Shen ,  Tak K. Lee

IPC分类号： H03M13/00

CPC分类号： H03M13/2957 ,  H03M13/6356 ,  H04L1/0041 ,  H04L1/0066 ,  H04L1/0067 ,  H04L1/0071

摘要： Turbo coding having combined turbo de-padding and rate matching de-padding. An approach is presented by which a singular module is operable to perform both zero bit de-padding and dummy bit de-padding in accordance with turbo encoding. Zero padding can be performed on an input information stream before undergoing turbo encoding. One or more of the 3 outputs from the turbo encoding module (e.g., systematic bits, parity 1 bits, and parity 2 bits) may then undergo dummy bit padding as well. Thereafter, these 3 streams (some or all of which may have undergone dummy bit padding) undergo sub-block interleaving. After all of these operations have taken place, a singular combined de-padding module that can be employed to perform de-padding any zero padded bits and any dummy padded bits from each of the three streams that have undergone the sub-block interleaving.

摘要翻译： Turbo编码具有组合的turbo去填充和速率匹配去填充。 提出了一种方法，通过该方法，单个模块可操作以根据turbo编码执行零比特解除填充和伪比特解除填充。 在进行turbo编码之前，可以对输入信息流执行零填充。 来自turbo编码模块的3个输出中的一个或多个（例如，系统比特，奇偶校验1比特和奇偶校验2比特）然后也可以经历伪比特填充。 此后，这3个流（其中一些或全部可能经历了伪位填充）经历子块交织。 在所有这些操作已经发生之后，可以采用单一组合的去填充模块来执行从填充子块交错的三个流中的每一个中去除任何零填充位和任何虚拟填充位。

公开(公告)号：US07831894B2

公开(公告)日：2010-11-09

申请号：US11810989

申请日：2007-06-07

申请人： Tak K. Lee ,  Ba-Zhong Shen

发明人： Tak K. Lee ,  Ba-Zhong Shen

IPC分类号： H03M13/03

CPC分类号： H03M13/2771 ,  H03M13/276 ,  H03M13/2957 ,  H03M13/6561 ,  H04L1/005 ,  H04L1/0066

摘要： Address generation for contention-free memory mappings of turbo codes with ARP (almost regular permutation) interleaves. A novel means is presented by which anticipatory address generation is employed using an index function that is based on an address mapping which corresponds to an interleave inverse order of decoding processing (π−1). In accordance with parallel turbo decoding processing, instead of performing the natural order phase decoding processing by accessing data elements from memory bank locations sequentially, the accessing of addresses is performed based on the index function that is based on an mapping and the interleave (π) employed within the turbo coding. In other words, the accessing data elements from memory bank locations is not sequential for natural order phase decoding processing. The index function also allows for the interleave (π) order phase decoding processing to be performed by accessing data elements from memory bank locations sequentially.

摘要翻译： 具有ARP（几乎规则排列）交织的turbo码的无竞争内存映射的地址生成。 提出了一种新颖的方法，其中使用基于对应于解码处理（＆pgr; -1）的交织逆顺序的地址映射的索引函数来采用预期地址生成。 根据并行turbo解码处理，代替通过从存储器单元顺序访问数据元素来执行自然次序相位解码处理，基于基于映射和交织（＆pgr）的索引函数来执行地址的访问。 ）。 换句话说，来自存储体位置的访问数据元素对于自然顺序相位解码处理不是顺序的。 索引函数还允许通过从存储体位置顺序地访问数据元素来进行交织（＆amp;）顺序相位解码处理。

公开(公告)号：US07752529B2

公开(公告)日：2010-07-06

申请号：US11493342

申请日：2006-07-26

申请人： Tak K. Lee ,  Ba-Zhong Shen

发明人： Tak K. Lee ,  Ba-Zhong Shen

IPC分类号： H03M13/00

CPC分类号： H03M13/1105 ,  H03M13/6502

摘要： Combined LDPC (Low Density Parity Check) encoder and syndrome checker. A novel approach is presented by which the encoding processing and at least a portion of the decoding processing of an LDPC coded signal can be performed using a shared circuitry. The LDPC encoding processing and syndrome calculation operations (in accordance with the LDPC decoding processing) can be performed using a common circuitry having a portion of which whose connectivity is only slightly modified depending on whether encoding or decoding is being performed. To effectuate this selection (between encoding and decoding), any of a variety of means can be employed including the use of multiplexers that are operable to select a first connectivity (for encoding) and a second connectivity (for decoding). This can result in a hardware savings of space, cost, and complexity since a shared circuitry can perform both encoding and at least part of the decoding processing.

摘要翻译： 组合LDPC（低密度奇偶校验）编码器和综合检查器。 提出了一种新颖的方法，通过该方法可以使用共享电路来执行LDPC编码信号的编码处理和至少一部分解码处理。 可以使用具有其部分连接性的公共电路来执行LDPC编码处理和校正子计算操作（根据LDPC解码处理），该部分的连接仅根据正在执行编码或解码而略微修改。 为了实现该选择（在编码和解码之间），可以采用各种手段中的任一种，包括使用可操作以选择第一连接（用于编码）和第二连接（用于解码）的多路复用器。 这可以导致空间，成本和复杂性的硬件节省，因为共享电路可以执行编码和至少部分解码处理。

公开(公告)号：US20100077277A1

公开(公告)日：2010-03-25

申请号：US12556379

申请日：2009-09-09

申请人： Ba-Zhong Shen ,  Tak K. Lee

发明人： Ba-Zhong Shen ,  Tak K. Lee

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： H03M13/116 ,  H03M13/033 ,  H03M13/1137 ,  H03M13/118 ,  H03M13/1185 ,  H03M13/635 ,  H03M13/6516 ,  H03M13/6527 ,  H03M13/6544 ,  H03M13/6561

摘要： Multi-CSI (Cyclic Shifted Identity) sub-matrix based LDPC (Low Density Parity Check) codes. A CSI parameter set, that includes at least one dual-valued entry and may also include at least one single-valued entry, and/or at least one all-zero-valued entry, is employed to generate an LDPC matrix. One of the single-valued entries may be 0 (being used to generate a CSI matrix with cyclic shift value of 0, corresponding to an identity sub-matrix such that all entries along the diagonal have elements values of 1, and all other elements therein are 0). Once the LDPC matrix is generated, it is employed to decode an LDPC coded signal to make an estimate of an information bit encoded therein. Also, the LDPC matrix may itself be used as an LDPC generator matrix (or the LDPC generator matrix may alternatively be generated by processing the LDPC matrix) for use in encoding an information bit.

摘要翻译： 多CSI（循环移位身份）基于子矩阵的LDPC（低密度奇偶校验）码。 使用包括至少一个双值条目并且还可以包括至少一个单值条目和/或至少一个全零值条目的CSI参数集合来生成LDPC矩阵。 单值条目中的一个可以是0（用于生成具有循环移位值0的CSI矩阵，对应于身份子矩阵，使得沿着对角线的所有条目具有元素值1，并且其中所有其他元素 是0）。 一旦生成了LDPC矩阵，就采用LDPC编码信号进行解码，对其中编码的信息比特进行估计。 此外，LDPC矩阵本身可以用作LDPC生成器矩阵（或者可替换地，LDPC生成器矩阵可以通过处理LDPC矩阵来生成）用于对信息比特进行编码。

公开(公告)号：US20090063940A1

公开(公告)日：2009-03-05

申请号：US11860679

申请日：2007-09-25

申请人： Johnson Yen ,  Ba-Zhong Shen ,  Tak K. Lee

发明人： Johnson Yen ,  Ba-Zhong Shen ,  Tak K. Lee

IPC分类号： H03M13/41

CPC分类号： H03M13/3955 ,  H03M13/4107 ,  H03M13/4146

摘要： A means is presented by which two trellis stages can be processes simultaneously and in parallel with one another (e.g., during a single clock cycle) thereby significantly increasing data throughput. Any one or more modules within a REX module can be implemented using a radix-4 architecture to increase data throughput. For example, any or more of a SMU (Survivor Memory Unit), a PED (Path Equivalency Detector), and a RMU (Reliability Measure Unit) can be implemented in accordance with the principles of radix-4 decoding processing.

摘要翻译： 提出了一种手段，其中两个网格级可以是彼此同时和并行处理（例如，在单个时钟周期内），从而显着增加数据吞吐量。 REX模块中的任何一个或多个模块可以使用基数4架构来实现，以增加数据吞吐量。 例如，可以根据基数-4解码处理的原理来实现SMU（幸存者存储器单元），PED（路径等效性检测器）和RMU（可靠性测量单元）中的任何一个或多个。