公开(公告)号：US10886250B2

公开(公告)日：2021-01-05

申请号：US15336192

申请日：2016-10-27

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00

Abstract: A method of making an assembly can include juxtaposing a top surface of a first electrically conductive element at a first surface of a first substrate with a top surface of a second electrically conductive element at a major surface of a second substrate. One of: the top surface of the first conductive element can be recessed below the first surface, or the top surface of the second conductive element can be recessed below the major surface. Electrically conductive nanoparticles can be disposed between the top surfaces of the first and second conductive elements. The conductive nanoparticles can have long dimensions smaller than 100 nanometers. The method can also include elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles can cause metallurgical joints to form between the juxtaposed first and second conductive elements.

公开(公告)号：US20200235085A1

公开(公告)日：2020-07-23

申请号：US16840245

申请日：2020-04-03

Applicant: Invensas Corporation

Inventor： Min Tao ,  Liang Wang ,  Rajesh Katkar ,  Cyprian Emeka Uzoh

IPC: H01L25/16 ,  H01L23/00 ,  H01L21/02 ,  H01L21/321 ,  H01L25/18 ,  H01L27/15 ,  H01L27/12 ,  H01L25/10 ,  H01L33/00

Abstract: Direct-bonded LED arrays and applications are provided. An example process fabricates a LED structure that includes coplanar electrical contacts for p-type and n-type semiconductors of the LED structure on a flat bonding interface surface of the LED structure. The coplanar electrical contacts of the flat bonding interface surface are direct-bonded to electrical contacts of a driver circuit for the LED structure. In a wafer-level process, micro-LED structures are fabricated on a first wafer, including coplanar electrical contacts for p-type and n-type semiconductors of the LED structures on the flat bonding interface surfaces of the wafer. At least the coplanar electrical contacts of the flat bonding interface are direct-bonded to electrical contacts of CMOS driver circuits on a second wafer. The process provides a transparent and flexible micro-LED array display, with each micro-LED structure having an illumination area approximately the size of a pixel or a smallest controllable element of an image represented on a high-resolution video display.

公开(公告)号：US10586759B2

公开(公告)日：2020-03-10

申请号：US16017010

申请日：2018-06-25

Applicant: Invensas Corporation

Inventor： Hong Shen ,  Liang Wang ,  Gabriel Z. Guevara ,  Rajesh Katkar ,  Cyprian Emeka Uzoh ,  Laura Wills Mirkarimi

IPC: H01L23/498 ,  H01L25/065 ,  H01L21/48 ,  H01L25/00 ,  H01L23/00

Abstract: An interposer (110) has contact pads at the top and/or bottom surfaces for connection to circuit modules (e.g. ICs 112). The interposer includes a substrate made of multiple layers (110.i). Each layer can be a substrate (110S), possibly a ceramic substrate, with circuitry. The substrates extend vertically. Multiple interposers are fabricated in a single structure (310) made of vertical layers (310.i) corresponding to the interposers' layers. The structure is diced along horizontal planes (314) to provide the interposers. An interposer's vertical conductive lines (similar to through-substrate vias) can be formed on the substrates' surfaces before dicing and before all the substrates are attached to each other. Thus, there is no need to make through-substrate holes for the vertical conductive lines. Non-vertical features can also be formed on the substrates' surfaces before the substrates are attached to each other. Other embodiments are also provided.

公开(公告)号：US10535626B2

公开(公告)日：2020-01-14

申请号：US15937149

申请日：2018-03-27

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh

IPC: H01L23/488 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

Abstract: A method of making an assembly can include juxtaposing a top surface of a first electrically conductive element at a first surface of a first substrate with a top surface of a second electrically conductive element at a major surface of a second substrate. One of: the top surface of the first conductive element can be recessed below the first surface, or the top surface of the second conductive element can be recessed below the major surface. Electrically conductive nanoparticles can be disposed between the top surfaces of the first and second conductive elements. The conductive nanoparticles can have long dimensions smaller than 100 nanometers. The method can also include elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles can cause metallurgical joints to form between the juxtaposed first and second conductive elements.

公开(公告)号：US10535564B2

公开(公告)日：2020-01-14

申请号：US15649457

申请日：2017-07-13

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh ,  Guilian Gao ,  Liang Wang ,  Hong Shen ,  Arkalgud R. Sitaram

IPC: H01L21/82 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L21/48 ,  H01L23/538

Abstract: A device and method of forming the device that includes cavities formed in a substrate of a substrate device, the substrate device also including conductive vias formed in the substrate. Chip devices, wafers, and other substrate devices can be mounted to the substrate device. Encapsulation layers and materials may be formed over the substrate device in order to fill the cavities.

公开(公告)号：US20190355683A1

公开(公告)日：2019-11-21

申请号：US16528354

申请日：2019-07-31

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh

IPC: H01L23/00 ,  H01L25/00 ,  H01L21/768 ,  H01L23/48

Abstract: An apparatus relating generally to a substrate is disclosed. In this apparatus, a post extends from the substrate. The post includes a conductor member. An upper portion of the post extends above an upper surface of the substrate. An exterior surface of the post associated with the upper portion is in contact with a dielectric layer. The dielectric layer is disposed on the upper surface of the substrate and adjacent to the post to provide a dielectric collar for the post. An exterior surface of the dielectric collar is in contact with a conductor layer. The conductor layer is disposed adjacent to the dielectric collar to provide a metal collar for the post, where a top surface of each of the conductor member, the dielectric collar and the metal collar have formed thereon a bond structure for interconnection of the metal collar and the conductor member.

公开(公告)号：US10475726B2

公开(公告)日：2019-11-12

申请号：US16037519

申请日：2018-07-17

Applicant: Invensas Corporation

Inventor： Rajesh Katkar ,  Cyprian Emeka Uzoh

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L21/683 ,  H01L23/373

Abstract: A component such as an interposer or microelectronic element can be fabricated with a set of vertically extending interconnects of wire bond structure. Such method may include forming a structure having wire bonds extending in an axial direction within one of more openings in an element and each wire bond spaced at least partially apart from a wall of the opening within which it extends, the element consisting essentially of a material having a coefficient of thermal expansion (“CTE”) of less than 10 parts per million per degree Celsius (“ppm/° C.”). First contacts can then be provided at a first surface of the component and second contacts provided at a second surface of the component facing in a direction opposite from the first surface, the first contacts electrically coupled with the second contacts through the wire bonds.

公开(公告)号：US20190304904A1

公开(公告)日：2019-10-03

申请号：US16446822

申请日：2019-06-20

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh ,  Zhuowen Sun

IPC: H01L23/522 ,  H01L23/14 ,  H01L23/48 ,  H01L23/498 ,  H01L21/768 ,  H01L21/48

Abstract: An interconnection component includes a semiconductor material layer having a first surface and a second surface opposite the first surface and spaced apart in a first direction. At least two metalized vias extend through the semiconductor material layer. A first pair of the at least two metalized vias are spaced apart from each other in a second direction orthogonal to the first direction. A first insulating via in the semiconductor layer extends from the first surface toward the second surface. The insulating via is positioned such that a geometric center of the insulating via is between two planes that are orthogonal to the second direction and that pass through each of the first pair of the at least two metalized vias. A dielectric material at least partially fills the first insulating via or at least partially encloses a void in the insulating via.

公开(公告)号：US10332833B2

公开(公告)日：2019-06-25

申请号：US16041013

申请日：2018-07-20

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh ,  Zhuowen Sun

IPC: H01L21/48 ,  H01L23/14 ,  H01L23/48 ,  H01L21/768 ,  H01L23/498 ,  H01L23/522

Abstract: An interconnection component includes a semiconductor material layer having a first surface and a second surface opposite the first surface and spaced apart in a first direction. At least two metalized vias extend through the semiconductor material layer. A first pair of the at least two metalized vias are spaced apart from each other in a second direction orthogonal to the first direction. A first insulating via in the semiconductor layer extends from the first surface toward the second surface. The insulating via is positioned such that a geometric center of the insulating via is between two planes that are orthogonal to the second direction and that pass through each of the first pair of the at least two metalized vias. A dielectric material at least partially fills the first insulating via or at least partially encloses a void in the insulating via.

公开(公告)号：US20190148344A1

公开(公告)日：2019-05-16

申请号：US16245116

申请日：2019-01-10

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh ,  Rajesh Katkar

IPC: H01L25/065 ,  H01L49/02 ,  H01L23/00 ,  H01L25/00 ,  H01L25/16 ,  H01L23/538 ,  H01L23/522 ,  H01L23/42 ,  H01L23/367 ,  H01L21/48 ,  H01L23/498 ,  H01L23/48 ,  B81B7/00

Abstract: Apparatus(es) and method(s) relate generally to via arrays on a substrate. In one such apparatus, the substrate has a conductive layer. First plated conductors are in a first region extending from a surface of the conductive layer. Second plated conductors are in a second region extending from the surface of the conductive layer. The first plated conductors and the second plated conductors are external to the first substrate. The first region is disposed at least partially within the second region. The first plated conductors are of a first height. The second plated conductors are of a second height greater than the first height. A second substrate is coupled to first ends of the first plated conductors. The second substrate has at least one electronic component coupled thereto. A die is coupled to second ends of the second plated conductors. The die is located over the at least one electronic component.