公开(公告)号：US20230009642A1

公开(公告)日：2023-01-12

申请号：US17369869

申请日：2021-07-07

Applicant: Micron Technology, Inc.

Inventor： Sean S. Eilert ,  Justin Eno ,  Ameen D. Akel

IPC: G06F3/06 ,  H03M13/09 ,  H03M13/11

Abstract: Methods, systems, and devices for programmable metadata and related operations are described. A method may include receiving signaling that indicates a set of rules for transitions of states of metadata at a memory device storing the metadata. The memory device may receive a command from a host device associated with a set of data after receiving the set of rules. The memory device may transition metadata associated with the set of data stored at the memory device from a first state to a second state based in part on the set of rules and the command. The memory device may execute the command received from the host device.

公开(公告)号：US20220382609A1

公开(公告)日：2022-12-01

申请号：US17886253

申请日：2022-08-11

Applicant: Micron Technology, Inc.

Inventor： Ameen D. Akel ,  Sean S. Eilert

IPC: G06F11/07 ,  G06F11/10 ,  G11C15/04 ,  G11C5/06 ,  G11C11/409

Abstract: Methods, systems, and devices for error control for content-addressable memory (CAM) are described. A CAM may store bit vectors as a set of subvectors, which each subvector stored in an independent aspect of the CAM, such as in a separate column or array of memory cells within the CAM. The CAM may similarly segment a queried input bit vector and identify, for each resulting input subvector, whether a matching subvector is stored by the CAM. The CAM may identify a match for the input bit vector when the number of matching subvectors satisfies a threshold. The CAM may validate a match based on comparing a stored bit vector corresponding to the identified match to the input bit vector. The stored bit vector may undergo error correction and may be stored in the CAM or another memory array, such as a dynamic random access memory (DRAM) array.

公开(公告)号：US11373695B2

公开(公告)日：2022-06-28

申请号：US16719907

申请日：2019-12-18

Applicant: Micron Technology, Inc.

Inventor： Shivam Swami ,  Sean S. Eilert ,  Ameen D. Akel

IPC: G11C11/22

Abstract: Methods, systems, and devices for memory accessing with auto-precharge are described. For example, a memory system may be configured to support an activate with auto-precharge command, which may be associated with a memory device opening a page of memory cells, latching respective logic states stored by the memory cells at a row buffer, writing logic states back to the page of memory cells, and maintaining the latched logic states at the row buffer (e.g., while maintaining power to latches of the row buffer, after closing the page of memory cells, while the page of memory cells is closed).

公开(公告)号：US20220121570A1

公开(公告)日：2022-04-21

申请号：US17100453

申请日：2020-11-20

Applicant: Micron Technology, Inc.

Inventor： Sean S. Eilert ,  Ameen D. Akel ,  Shivam Swami

IPC: G06F12/0802 ,  G06F3/06

Abstract: An example memory sub-system includes: a plurality of bank groups, wherein each bank group comprises a plurality of memory banks; a plurality of row buffers, wherein two or more row buffers of the plurality of row buffers are associated with each memory bank; a cache comprising a plurality of cache lines; a processing logic communicatively coupled to the plurality of bank groups and the plurality of row buffers, the processing logic to perform operations comprising: receiving an activate command specifying a row of a memory bank of the plurality of memory banks; fetching data from the specified row to a row buffer of the plurality of row buffers; and copying the data to a cache line of the plurality of cache lines.

公开(公告)号：US11169930B2

公开(公告)日：2021-11-09

申请号：US16424427

申请日：2019-05-28

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov ,  Ameen D. Akel ,  Samuel E. Bradshaw ,  Kenneth Marion Curewitz ,  Sean Stephen Eilert

IPC: G06F12/1009 ,  G06F12/1027 ,  G06N5/04 ,  H04L29/08 ,  H04W8/26

Abstract: Systems, methods and apparatuses of fine grain data migration in using Memory as a Service (MaaS) are described. For example, a memory status map can be used to identify the cache availability of sub-regions (e.g., cache lines) of a borrowed memory region (e.g., a borrowed remote memory page). Before accessing a virtual memory address in a sub-region, the memory status map is checked. If the sub-region has cache availability in the local memory, the memory management unit uses a physical memory address converted from the virtual memory address to make memory access. Otherwise, the sub-region is cached from the borrowed memory region to the local memory, before the physical memory address is used.

公开(公告)号：US11100007B2

公开(公告)日：2021-08-24

申请号：US16424420

申请日：2019-05-28

Applicant: Micron Technology, Inc.

Inventor： Samuel E. Bradshaw ,  Ameen D. Akel ,  Kenneth Marion Curewitz ,  Sean Stephen Eilert ,  Dmitri Yudanov

IPC: G06F12/1027 ,  H04L29/08 ,  H04W84/04

Abstract: Systems, methods and apparatuses to accelerate accessing of borrowed memory over network connection are described. For example, a memory management unit (MMU) of a computing device can be configured to be connected both to the random access memory over a memory bus and to a computer network via a communication device. The computing device can borrow an amount of memory from a remote device over a network connection using the communication device; and applications running in the computing device can use virtual memory addresses mapped to the borrowed memory. When a virtual address mapped to the borrowed memory is used, the MMU translates the virtual address into a physical address and instruct the communication device to access the borrowed memory.

公开(公告)号：US20210240398A1

公开(公告)日：2021-08-05

申请号：US17236981

申请日：2021-04-21

Applicant: Micron Technology, Inc.

Inventor： Shivasankar Gunasekaran ,  Samuel E. Bradshaw ,  Justin M. Eno ,  Ameen D. Akel

IPC: G06F3/06 ,  G06F12/0873 ,  G06F11/07

Abstract: A memory sub-system configured to be responsive to a time to live requirement for load commands from a processor. For example, a load command issued by the processor (e.g., SoC) can include, or be associated with, an optional time to live parameter. The parameter requires that the data at the memory address be available within the time specified by the time to live parameter. When the requested data is currently in the lower speed memory (e.g., NAND flash) and not available in the higher speed memory (e.g., DRAM, NVRAM), the memory sub-system can determine that the data cannot be made available with the specified time and optionally skip the operations and return an error response immediately.

公开(公告)号：US20210165609A1

公开(公告)日：2021-06-03

申请号：US17175911

申请日：2021-02-15

Applicant: Micron Technology, Inc.

Inventor： Ameen D. Akel ,  Sean S. Eilert

IPC: G06F3/06 ,  G11C15/04 ,  G11C13/00

Abstract: An apparatus (e.g., a content addressable memory system) can have a controller, a first content addressable memory coupled to the controller, and a second content addressable memory coupled to the controller. The controller can be configured to cause the first content addressable memory to write data in the first content addressable memory, cause the second content addressable memory to write the data in the second content addressable memory, and cause the second content addressable memory to query the data written in the second content addressable memory while the first content addressable memory continues to write the data in the first content addressable memory.

公开(公告)号：US20210081141A1

公开(公告)日：2021-03-18

申请号：US16573785

申请日：2019-09-17

Applicant: Micron Technology, Inc.

Inventor： Kenneth Marion Curewitz ,  Shivam Swami ,  Samuel E. Bradshaw ,  Justin M. Eno ,  Ameen D. Akel ,  Sean S. Eilert

IPC: G06F3/06 ,  G06F12/02 ,  H01L27/24

Abstract: A memory chip having a predefined memory region configured to store program data transmitted from a microchip. The memory chip also having a programmable engine configured to facilitate access to a second memory chip to read data from the second memory chip and write data to the second memory chip according to stored program data in the predefined memory region. The predefined memory region can include a portion configured as a command queue for the programmable engine, and the programmable engine can be configured to facilitate access to the second memory chip according to the command queue.

公开(公告)号：US20210072957A1

公开(公告)日：2021-03-11

申请号：US16888345

申请日：2020-05-29

Applicant: Micron Technology, Inc.

Inventor： Sean S. Eilert ,  Shivasankar Gunasekaran ,  Ameen D. Akel ,  Dmitri Yudanov ,  Sivagnanam Parthasarathy

IPC: G06F7/544 ,  G06F17/16

Abstract: Systems, apparatuses, and methods of operating memory systems are described. Processing-in-memory capable memory devices are also described, and methods of performing fused-multiply-add operations within the same. Bit positions of bits stored at one or more portions of one or more memory arrays, may be accessed via data lines by activating the same or different access lines. A sensing circuit operatively coupled to a data line may be temporarily formed and measured to determine a state (e.g., a count of the number of bits that are a logic “1”) of accessed bit positions of a data line, and state information may be used to determine a computational result.