公开(公告)号：US5822559A

公开(公告)日：1998-10-13

申请号：US582473

申请日：1996-01-02

Applicant: Rammohan Narayan ,  Thang M. Tran

Inventor： Rammohan Narayan ,  Thang M. Tran

IPC: G06F9/30 ,  G06F9/318 ,  G06F9/38

CPC classification number: G06F9/3017 ,  G06F9/30054 ,  G06F9/30152 ,  G06F9/3806 ,  G06F9/3816 ,  G06F9/382 ,  G06F9/3822

Abstract: A microprocessor is provided, including a plurality of early decode units configured to detect double dispatch instructions and to dispatch these instructions to a pair of decode units. More complex instructions are executed by an MROM unit in a serialized fashion. Simpler instructions are dispatched to a single decode unit. The early decode units partially decode the instructions (including encoding the instruction prefix into a single prefix byte), and the decoding is completed by a plurality of decode units. The present microprocessor additionally detects the more complex instructions prior to instruction decode and dispatches the instructions to an MROM unit.

Abstract translation: 提供了一种微处理器，包括多个早期解码单元，其被配置为检测双重分派指令并将这些指令分派到一对译码单元。 更复杂的指令由MROM单元以串行方式执行。 更简单的指令被分派到单个解码单元。 早期解码单元部分地解码指令（包括将指令前缀编码为单个前缀字节），并且解码由多个解码单元完成。 本微处理器在指令解码之前还附加地检测更复杂的指令，并将指令分派到MROM单元。

公开(公告)号：US5787266A

公开(公告)日：1998-07-28

申请号：US603805

申请日：1996-02-20

Applicant: William M. Johnson ,  Thang M. Tran ,  Rupaka Mahalingaiah

Inventor： William M. Johnson ,  Thang M. Tran ,  Rupaka Mahalingaiah

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/00

CPC classification number: G06F9/30167 ,  G06F9/30101 ,  G06F9/30152 ,  G06F9/30163 ,  G06F9/382 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

Abstract: A microprocessor employing an apparatus for performing special register writes without serialization is provided. The apparatus detects special register write instructions when the instructions are dispatched, and stores an indication of the write in a special register dependency block. Instructions subsequent to the special register write instruction are examined for both explicit and implicit dependencies upon the special register write. If a dependency is detected with respect to a particular instruction, the instruction is dispatched to a reservation station along with an indication of the dependency. Instructions subsequent to the special register write instruction which are not dependent upon the special register are dispatched without an indication of special register dependency. Instructions without dependencies may speculatively execute prior to instructions with dependencies, or even prior to the special register write instruction. In one particular embodiment employing the x86 microprocessor architecture, the microprocessor detects updates to the DS, ES, FS, and GS segment registers (i.e. the data segment registers). Updates to other segment registers are serialized.

Abstract translation: 提供了一种使用不进行串行化来执行特殊寄存器写入的装置的微处理器。 当调度指令时，该设备检测特殊寄存器写指令，并将写入的指示存储在特殊寄存器依赖块中。 在特殊寄存器写入指令之后的指令将针对特殊寄存器写入时的显式和隐式依赖性进行检查。 如果相对于特定指令检测到依赖关系，则将该指令与依赖性的指示一起发送到保留站。 在不依赖于特殊寄存器的特殊寄存器写入指令之后的指令被调度，而不指示特殊寄存器依赖性。 没有依赖性的指令可以在具有依赖性的指令之前，甚至在特殊寄存器写指令之前推测执行。 在采用x86微处理器架构的一个特定实施例中，微处理器检测对DS，ES，FS和GS段寄存器（即，数据段寄存器）的更新。 其他段寄存器的更新被序列化。

公开(公告)号：US5768553A

公开(公告)日：1998-06-16

申请号：US550024

申请日：1995-10-30

Applicant: Thang M. Tran

Inventor： Thang M. Tran

IPC: G06F9/318 ,  G06F9/38 ,  G06F9/30

CPC classification number: G06F9/30185 ,  G06F9/30167 ,  G06F9/3822 ,  G06F9/3879

Abstract: A microprocessor employing a DSP unit and an instruction decode unit is provided. The instruction decode unit is configured to detect an instruction field included with an instruction, and to dispatch instructions having the instruction field to the DSP unit. The DSP unit performs DSP functions, such as a multiply-accumulate function. In one embodiment, the inclusion of an instruction prefix field in an .times.86 instruction indicates that the instruction is a DSP instruction. In one particular implementation, the inclusion of a segment override prefix byte within the prefix field of an .times.86 instruction indicates that the instruction is a DSP instruction. Embodiments of the DSP unit may include a vector memory for storing operands. A block of operands may be stored into the vector memory prior to initiating a large number of DSP operations upon the block of operands.

Abstract translation: 提供了采用DSP单元和指令解码单元的微处理器。 指令解码单元被配置为检测包括在指令中的指令字段，并且将具有指令字段的指令分派给DSP单元。 DSP单元执行DSP功能，例如乘法累加功能。 在一个实施例中，在x86指令中包括指令前缀字段指示该指令是DSP指令。 在一个特定实现中，在x86指令的前缀字段内包括段重写前缀字节指示该指令是DSP指令。 DSP单元的实施例可以包括用于存储操作数的向量存储器。 在对操作数块进行大量DSP操作之前，操作数块可以被存储到向量存储器中。

公开(公告)号：US5713039A

公开(公告)日：1998-01-27

申请号：US567665

申请日：1995-12-05

Applicant: Thang M. Tran

Inventor： Thang M. Tran

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/34 ,  G06F12/00

CPC classification number: G06F9/30141 ,  G06F9/3012 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

Abstract: A register file including multiple register storages and multiple read ports is provided. Each register storage stores a subset of the architected register set for the microprocessor within which the register file is employed. Each register storage is coupled to select ones of the multiple read ports, reducing wiring and complexity of the register file. Each read port is coupled to a subset of the registers within the register file. The subset of the registers to which the read port is coupled is defined by the register storage(s) to which the read port is coupled. Access to a particular register is thereby restricted to a subset of the read ports coupled to the register file. However, for data access patterns such as the data access patterns characteristic of DSP functions, such restrictions may have an insignificant impact upon performance. The independent data streams of typical DSP functions may each be stored within one of the separate subsets of the architected register set, allowing the DSP functions to concurrently access the operands from each data stream using the present register file. One read port upon each of the register storages is utilized by an instruction from the DSP functions. Although the size and complexity of the register file are decreased with respect to conventional register files, full functionality may be provided for the DSP functions.

Abstract translation: 提供了包括多个寄存器存储器和多个读取端口的寄存器文件。 每个寄存器存储器存储用于使用寄存器文件的微处理器的架构化寄存器集的子集。 每个寄存器存储器耦合以选择多个读取端口中的一个，从而减少寄存器文件的布线和复杂性。 每个读端口耦合到寄存器文件中寄存器的子集。 读端口耦合到的寄存器的子集由读端口耦合到的寄存器存储器定义。 因此，对特定寄存器的访问被限制到耦合到寄存器文件的读取端口的子集。 然而，对于诸如DSP功能特征的数据访问模式的数据访问模式，这种限制可能对性能产生微不足道的影响。 典型DSP功能的独立数据流可以各自存储在架构化寄存器组的单独子集之一中，从而允许DSP功能使用本寄存器文件从每个数据流同时访问操作数。 每个寄存器存储器上的一个读端口由DSP功能的指令使用。 虽然寄存器文件的大小和复杂度相对于常规寄存器文件而减少，但是可以为DSP功能提供全部功能。

公开(公告)号：US5483645A

公开(公告)日：1996-01-09

申请号：US020370

申请日：1993-02-22

Applicant: Thang M. Tran

Inventor： Thang M. Tran

IPC: G06F12/08 ,  G06F13/18 ,  G06F13/16

CPC classification number: G06F12/0831 ,  G06F13/18 ,  G06F12/0857

Abstract: The present invention is an apparatus comprising first and second addressable arrays and an input for receiving address information related to the arrays. A first request line receives from a first source first request signals for access to the first and second arrays based on the address information. A second request line receives from a second source second request signals for access to the first and second arrays based on the address information. A processing circuit transmits the address information to the first and second addressable arrays in response to the first and second request signals based on a priority of the first and second request signals.

Abstract translation: 本发明是一种包括第一和第二可寻址阵列和用于接收与阵列相关的地址信息的输入的装置。 从第一源接收的第一请求线首先基于地址信息请求访问第一和第二阵列的信号。 第二请求线基于地址信息从第二源接收第二请求信号以访问第一和第二阵列。 处理电路基于第一和第二请求信号的优先级，响应于第一和第二请求信号将地址信息发送到第一和第二可寻址阵列。

公开(公告)号：US5251306A

公开(公告)日：1993-10-05

申请号：US465808

申请日：1990-01-16

Applicant: Thang M. Tran

Inventor： Thang M. Tran

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/382 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3842 ,  G06F9/3857

Abstract: An apparatus for controlling execution of a program of instructions in a computing device comprising an instruction fetching buffer-decoder for fetching the instructions in fetch batches and decoding the fetched instructions to generate a plurality of decoded instructions; an executing unit for executing the decoded instructions; and a storage unit including a plurality of registers for storing operand information. Each respective register includes at least one scoreboard bit indicating how the respective register is being used by the plurality of instructions; the execution unit effects execution of a specified instruction when a specified register containing operand information required by the specified instruction has a scoreboard bit having a specified value.

Abstract translation: 一种用于控制计算装置中的指令程序的执行的装置，包括获取缓冲器解码器的指令，用于取出取样批中的指令，并且解码所取出的指令以产生多个经解码的指令; 用于执行解码指令的执行单元; 以及包括用于存储操作数信息的多个寄存器的存储单元。 每个相应的寄存器包括至少一个记分板位，指示该多个指令如何使用相应的寄存器; 当包含指定指令所需的操作数信息的指定寄存器具有指定值的记分板位时，执行单元执行指定指令的执行。

公开(公告)号：US5185868A

公开(公告)日：1993-02-09

申请号：US464918

申请日：1990-01-16

Applicant: Thang M. Tran

Inventor： Thang M. Tran

IPC: G06F9/38

CPC classification number: G06F9/3822 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3842 ,  G06F9/3857

Abstract: An apparatus for use with a computing device for executing instructions in a logical sequence according to a control program, comprises an instruction buffer of FIFO construction serially connected to a decoder buffer also of a FIFO construction. The decoder buffer includes a number of decoder units arranged in a hierarchical manner from a lowest-significance decoder unit to a highest-significance decoder unit in order to maintain the logical sequence of the instructions. The decoder units concurrently decode instructions transmitted from the instruction buffer and concurrently determine whether a corresponding decoded instruction is ready to be sent to an instruction executing unit. Each decoder unit is capable of sending a corresponding instruction to the instruction executing unit. Instructions ready to be sent are sent to the instruction executing unit, according to the logical sequence. Instructions not ready to be sent are shifted to higher-significance available vacant decoder units, while maintaining the logical sequence of the instructions.

Abstract translation: 一种与计算装置一起使用的装置，用于根据控制程序执行逻辑序列中的指令，包括FIFO构造的指令缓冲器，其串行连接到FIFO构造的解码器缓冲器。 解码器缓冲器包括从最低有效译码器单元到最高有效译码器单元以分级方式布置的多个解码器单元，以便保持指令的逻辑顺序。 解码器单元同时解码从指令缓冲器发送的指令，并且同时确定相应的解码指令是否准备好发送到指令执行单元。 每个解码器单元能够向指令执行单元发送相应的指令。 根据逻辑顺序将准备发送的指令发送到指令执行单元。 不能准备发送的指令被转移到更高有效的空闲解码器单元，同时保持指令的逻辑顺序。