公开(公告)号：US11205710B2

公开(公告)日：2021-12-21

申请号：US16357333

申请日：2019-03-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Chien Hsieh ,  En-Chiuan Liou ,  Chih-Wei Yang ,  Yu-Cheng Tung ,  Po-Wen Su

IPC: H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/265 ,  H01L21/266 ,  H01L29/78

Abstract: A fabricating method of a semiconductor structure includes the following steps. A gate material layer is formed on a semiconductor substrate. A patterned mask layer is formed on the gate material layer. The pattern mask layer includes at least one opening exposing a part of the gate material layer. An impurity treatment is performed to the gate material layer partially covered by the pattern mask layer for forming at least one doped region in the gate material layer. An etching process is performed to remove the gate material layer including the doped region. A dummy gate may be formed by patterning the gate material layer, and the impurity treatment may be performed after the step of forming the dummy gate. The performance of the etching processes for removing the gate material layer and/or the dummy gate may be enhanced, and the gate material residue issue may be solved accordingly.

公开(公告)号：US10818660B2

公开(公告)日：2020-10-27

申请号：US16407188

申请日：2019-05-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung ,  Chih-Wei Yang

IPC: H01L27/088 ,  H01L21/762 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/78

Abstract: A manufacturing method of a semiconductor device includes the following steps. A semiconductor substrate including at least one fin structure is provided. A gate material layer is formed on the semiconductor substrate, and the fin structure is covered by the gate material layer. A trench is formed partly in the gate material layer and partly in the fin structure. An isolation structure is formed partly in the trench and partly outside the trench. At least one gate structure is formed straddling the fin structure by patterning the gate material layer after the step of forming the isolation structure. A top surface of the isolation structure is higher than a top surface of the gate structure in a vertical direction for enhancing the isolation performance of the isolation structure. A sidewall spacer is formed on sidewalls of the isolation structure, and there is no gate structure formed on the isolation structure.

公开(公告)号：US10790202B2

公开(公告)日：2020-09-29

申请号：US16368795

申请日：2019-03-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L21/66 ,  H01L23/544 ,  G03F7/20

Abstract: The present invention provides an overlay mark, including a substrate and plural sets of first pattern block and second pattern block. A first direction and a second direction are defined on the substrate, wherein the first direction and the second direction are perpendicular to each other. In each set, the first pattern block is rotational symmetrical to the second pattern block. Each first pattern block includes a big frame and plural small frame. Each second pattern block includes a big frame and plural small frame. The width of the big frame is greater than three times of the width of the small frame. The present invention further provides a method for evaluating the stability of a semiconductor manufacturing process.

公开(公告)号：US10600692B2

公开(公告)日：2020-03-24

申请号：US16200670

申请日：2018-11-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsiao-Lin Hsu ,  En-Chiuan Liou

IPC: H01L21/8234 ,  H01L29/78 ,  H01L27/088 ,  H01L29/40 ,  H01L29/66

Abstract: A semiconductor device includes a substrate having a fin structure extending along a first direction. The fin structure protrudes from a top surface of a trench isolation region and has a first height. A plurality of gate lines including a first gate line and a second gate line extend along a second direction and striding across the fin structure. The first gate line has a discontinuity directly above a gate cut region. The second gate line is disposed in proximity to a dummy fin region, and does not overlap with the dummy fin region. The fin structure has a second height within the dummy fin region, and the second height is smaller than the first height.

公开(公告)号：US10571796B2

公开(公告)日：2020-02-25

申请号：US15585000

申请日：2017-05-02

Applicant: United Microelectronics Corp.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: G03F1/24 ,  G03F1/52 ,  G03F1/54 ,  G03F1/80

Abstract: An extreme ultraviolet (EUV) photomask includes a mask substrate, a reflection layer and a light-absorbing pattern layer. The reflection layer is disposed on the mask substrate, wherein the reflection layer has a concave pattern. The light-absorbing pattern layer is in the reflection layer, to fill the concave pattern. The light-absorbing pattern layer is exposed.

公开(公告)号：US10522415B1

公开(公告)日：2019-12-31

申请号：US16562454

申请日：2019-09-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung ,  Chih-Wei Yang

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/06 ,  H01L27/12 ,  H01L21/84 ,  H01L29/66 ,  H01L21/82

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, an isolation structure, and a source/drain region. The semiconductor substrate includes a fin. The gate structure is disposed on the fin and is disposed straddling the fin. The isolation structure covers a sidewall and a top surface of the fin. The source/drain region is disposed in the fin and extends beyond the top surface of the fin.

公开(公告)号：US10453849B2

公开(公告)日：2019-10-22

申请号：US15936396

申请日：2018-03-26

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung ,  Chih-Wei Yang ,  Sho-Shen Lee

IPC: H01L29/02 ,  H01L27/108 ,  G11C11/401

Abstract: The present invention provides a dynamic random access memory structure, comprising a substrate defining a cell region and a peripheral region on the substrate, a shallow trench isolation structure located in the peripheral region adjacent to the cell region, wherein the shallow trench isolation structure has a concave top surface, a first dummy bit line gate located within the shallow trench isolation structure of the peripheral area, and a second dummy bit line gate located in the cell region and adjacent to the first dummy bit line gate, wherein a top surface of the first dummy bit line gate is lower than a top surface of the second dummy bit line gate.

公开(公告)号：US10431457B2

公开(公告)日：2019-10-01

申请号：US15361085

申请日：2016-11-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: G03F1/70 ,  H01L21/027 ,  G03F7/00 ,  G03F7/20

Abstract: A method for forming a patterned structure includes following steps. First lines elongated in a first direction and second lines elongated in a second direction in a layout pattern are decomposed into two masks. A first mask includes first line patterns and a first block pattern. A second mask includes second line patterns and a second block pattern. Two photolithography processes with the first mask and the second mask are performed for forming a patterned structure including first line structures and second line structures. Each first line structure is elongated in the first direction. The first line structures are defined by a region where the first line patterns and the second block pattern overlap with one another. Each second line structure is elongated in the second direction. The second line structures are defined by a region where the second line patterns and the first block pattern overlap with one another.

公开(公告)号：US10373915B1

公开(公告)日：2019-08-06

申请号：US16202104

申请日：2018-11-28

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Hsiao-Lin Hsu ,  En-Chiuan Liou ,  Yi-Ting Chen ,  Sho-Shen Lee

IPC: H01L23/544 ,  H01L21/66 ,  G01B11/27 ,  H01L21/8234

Abstract: A measurement make includes four rectangular regions having a first region and a second region arranged diagonally, and a third region and a fourth region arranged diagonally. A plurality sets of first inner pattern blocks, first middle pattern blocks, and first outer reference pattern blocks, are disposed within the first region. Each first inner pattern block comprises line patterns and a block pattern. The block pattern has multiple space patterns arranged therein. The first inner pattern block is rotational symmetrical to the first middle pattern block.

公开(公告)号：US10283413B2

公开(公告)日：2019-05-07

申请号：US15264590

申请日：2016-09-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung ,  Chih-Wei Yang

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/08 ,  H01L21/84 ,  H01L27/12 ,  H01L29/66 ,  H01L21/82

Abstract: A semiconductor device includes a semiconductor substrate, an isolation structure, and a spacer. The semiconductor substrate includes at least one fin structure. The isolation structure is partly disposed in the fin structure and partly disposed above the fin structure. The fin structure includes a first fin and a second fin elongated in the same direction. A part of the isolation structure is disposed between the first fin and the second fin in the direction where the first fin and the second fin are elongated. The spacer is disposed on sidewalls of the isolation structure on the fin structure. The isolation structure in the present invention is partly disposed in the fin structure and partly disposed above the fin structure. The negative influence of a gate structure formed on the isolation structure and sinking into the isolation structure on the isolation performance of the isolation structure may be avoided accordingly.